计数器是数字电路系统中最基本的功能模块之一，设计时可以采用原理图或HDL语言完成。

下载验证时的计数时钟可选用连续或单脉冲，并用数码管显示计数值。

-The counter is one of the basic function module in the digital circuit system, can be used in the design of the schematic or HDL language completed. The download validation count clock choice of continuous or single pulse and count value with digital display.