文件名称:lcd
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- 上传时间:2013-03-12
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文件大小:12.43mb
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基于fpga的lcd1602的verilog程序代码,可实现移动显示数字和英文字母-Verilog fpga lcd1602 the program code, mobile numbers and letters
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下载文件列表
lcd/db/lcd.(0).cnf.cdb
lcd/db/lcd.(0).cnf.hdb
lcd/db/lcd.amm.cdb
lcd/db/lcd.asm.qmsg
lcd/db/lcd.asm.rdb
lcd/db/lcd.asm_labs.ddb
lcd/db/lcd.cbx.xml
lcd/db/lcd.cmp.bpm
lcd/db/lcd.cmp.cdb
lcd/db/lcd.cmp.hdb
lcd/db/lcd.cmp.kpt
lcd/db/lcd.cmp.logdb
lcd/db/lcd.cmp.rdb
lcd/db/lcd.cmp_merge.kpt
lcd/db/lcd.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
lcd/db/lcd.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
lcd/db/lcd.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
lcd/db/lcd.db_info
lcd/db/lcd.eda.qmsg
lcd/db/lcd.fit.qmsg
lcd/db/lcd.hier_info
lcd/db/lcd.hif
lcd/db/lcd.idb.cdb
lcd/db/lcd.lpc.html
lcd/db/lcd.lpc.rdb
lcd/db/lcd.lpc.txt
lcd/db/lcd.map.bpm
lcd/db/lcd.map.cdb
lcd/db/lcd.map.hdb
lcd/db/lcd.map.kpt
lcd/db/lcd.map.logdb
lcd/db/lcd.map.qmsg
lcd/db/lcd.map_bb.cdb
lcd/db/lcd.map_bb.hdb
lcd/db/lcd.map_bb.logdb
lcd/db/lcd.pre_map.cdb
lcd/db/lcd.pre_map.hdb
lcd/db/lcd.rtlv.hdb
lcd/db/lcd.rtlv_sg.cdb
lcd/db/lcd.rtlv_sg_swap.cdb
lcd/db/lcd.sgdiff.cdb
lcd/db/lcd.sgdiff.hdb
lcd/db/lcd.sld_design_entry.sci
lcd/db/lcd.sld_design_entry_dsc.sci
lcd/db/lcd.smart_action.txt
lcd/db/lcd.smp_dump.txt
lcd/db/lcd.sta.qmsg
lcd/db/lcd.sta.rdb
lcd/db/lcd.sta_cmp.8_slow_1200mv_85c.tdb
lcd/db/lcd.syn_hier_info
lcd/db/lcd.tiscmp.fastest_slow_1200mv_0c.ddb
lcd/db/lcd.tiscmp.fastest_slow_1200mv_85c.ddb
lcd/db/lcd.tiscmp.fast_1200mv_0c.ddb
lcd/db/lcd.tiscmp.slow_1200mv_0c.ddb
lcd/db/lcd.tiscmp.slow_1200mv_85c.ddb
lcd/db/lcd.tis_db_list.ddb
lcd/db/lcd.tmw_info
lcd/db/logic_util_heursitic.dat
lcd/db/prev_cmp_lcd.qmsg
lcd/db
lcd/e1240.tcl
lcd/incremental_db/compiled_partitions/lcd.db_info
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.cdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.dfp
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.hdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.kpt
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.logdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.rcfdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.cdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.dpi
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.cdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.hb_info
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.hdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.sig
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.kpt
lcd/incremental_db/compiled_partitions
lcd/incremental_db/README
lcd/incremental_db
lcd/lcd.asm.rpt
lcd/lcd.cdf
lcd/lcd.done
lcd/lcd.eda.rpt
lcd/lcd.fit.rpt
lcd/lcd.fit.smsg
lcd/lcd.fit.summary
lcd/lcd.flow.rpt
lcd/lcd.map.rpt
lcd/lcd.map.summary
lcd/lcd.pin
lcd/lcd.qpf
lcd/lcd.qsf
lcd/lcd.sof
lcd/lcd.sta.rpt
lcd/lcd.sta.summary
lcd/lcd.v
lcd/lcd.v.bak
lcd/lcd_nativelink_simulation.rpt
lcd/lcd_tb.v
lcd/lcd_tb.v.bak
lcd/simulation/modelsim/lcd.sft
lcd/simulation/modelsim/lcd.vo
lcd/simulation/modelsim/lcd_8_1200mv_0c_slow.vo
lcd/simulation/modelsim/lcd_8_1200mv_0c_v_slow.sdo
lcd/simulation/modelsim/lcd_8_1200mv_85c_slow.vo
lcd/simulation/modelsim/lcd_8_1200mv_85c_v_slow.sdo
lcd/simulation/modelsim/lcd_min_1200mv_0c_fast.vo
lcd/simulation/modelsim/lcd_min_1200mv_0c_v_fast.sdo
lcd/simulation/modelsim/lcd_modelsim.xrf
lcd/simulation/modelsim/lcd_run_msim_rtl_verilog.do
lcd/simulation/modelsim/lcd_run_msim_rtl_verilog.do.bak
lcd/simulation/modelsim/lcd_run_msim_rtl_verilog.do.bak1
lcd/simulation/modelsim/lcd_v.sdo
lcd/simulation/modelsim/modelsim.ini
lcd/simulation/modelsim/msim_transcript
lcd/simulation/modelsim/rtl_work/lcd/verilog.prw
lcd/simulation/modelsim/rtl_work/lcd/verilog.psm
lcd/simulation/modelsim/rtl_work/lcd/_primary.dat
lcd/simulation/modelsim/rtl_work/lcd/_primary.dbs
lcd/simulation/modelsim/rtl_work/lcd/_primary.vhd
lcd/simulation/modelsim/rtl_work/lcd
lcd/simulation/modelsim/rtl_work/lcd_tb/verilog.prw
lcd/simulation/modelsim/rtl_work/lcd_tb/verilog.psm
lcd/simulation/modelsim/rtl_work/lcd_tb/_primary.dat
lcd/simulation/modelsim/rtl_work/lcd_tb/_primary.dbs
lcd/simulation/modelsim/rtl_work/lcd_tb/_primary.vhd
lcd/simulation/modelsim/rtl_work/lcd_tb
lcd/simulation/modelsim/rtl_work/_info
lcd/simulation/modelsim/rtl_work/_temp
lcd/simulation/modelsim/rtl_work/_vmake
lcd/simulation/modelsim/rtl_work
lcd/simulation/modelsim/vsim.wlf
lcd/simulation/modelsim
lcd/simulation
lcd
lcd/db/lcd.(0).cnf.hdb
lcd/db/lcd.amm.cdb
lcd/db/lcd.asm.qmsg
lcd/db/lcd.asm.rdb
lcd/db/lcd.asm_labs.ddb
lcd/db/lcd.cbx.xml
lcd/db/lcd.cmp.bpm
lcd/db/lcd.cmp.cdb
lcd/db/lcd.cmp.hdb
lcd/db/lcd.cmp.kpt
lcd/db/lcd.cmp.logdb
lcd/db/lcd.cmp.rdb
lcd/db/lcd.cmp_merge.kpt
lcd/db/lcd.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
lcd/db/lcd.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
lcd/db/lcd.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
lcd/db/lcd.db_info
lcd/db/lcd.eda.qmsg
lcd/db/lcd.fit.qmsg
lcd/db/lcd.hier_info
lcd/db/lcd.hif
lcd/db/lcd.idb.cdb
lcd/db/lcd.lpc.html
lcd/db/lcd.lpc.rdb
lcd/db/lcd.lpc.txt
lcd/db/lcd.map.bpm
lcd/db/lcd.map.cdb
lcd/db/lcd.map.hdb
lcd/db/lcd.map.kpt
lcd/db/lcd.map.logdb
lcd/db/lcd.map.qmsg
lcd/db/lcd.map_bb.cdb
lcd/db/lcd.map_bb.hdb
lcd/db/lcd.map_bb.logdb
lcd/db/lcd.pre_map.cdb
lcd/db/lcd.pre_map.hdb
lcd/db/lcd.rtlv.hdb
lcd/db/lcd.rtlv_sg.cdb
lcd/db/lcd.rtlv_sg_swap.cdb
lcd/db/lcd.sgdiff.cdb
lcd/db/lcd.sgdiff.hdb
lcd/db/lcd.sld_design_entry.sci
lcd/db/lcd.sld_design_entry_dsc.sci
lcd/db/lcd.smart_action.txt
lcd/db/lcd.smp_dump.txt
lcd/db/lcd.sta.qmsg
lcd/db/lcd.sta.rdb
lcd/db/lcd.sta_cmp.8_slow_1200mv_85c.tdb
lcd/db/lcd.syn_hier_info
lcd/db/lcd.tiscmp.fastest_slow_1200mv_0c.ddb
lcd/db/lcd.tiscmp.fastest_slow_1200mv_85c.ddb
lcd/db/lcd.tiscmp.fast_1200mv_0c.ddb
lcd/db/lcd.tiscmp.slow_1200mv_0c.ddb
lcd/db/lcd.tiscmp.slow_1200mv_85c.ddb
lcd/db/lcd.tis_db_list.ddb
lcd/db/lcd.tmw_info
lcd/db/logic_util_heursitic.dat
lcd/db/prev_cmp_lcd.qmsg
lcd/db
lcd/e1240.tcl
lcd/incremental_db/compiled_partitions/lcd.db_info
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.cdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.dfp
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.hdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.kpt
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.logdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.cmp.rcfdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.cdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.dpi
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.cdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.hb_info
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.hdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hbdb.sig
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.hdb
lcd/incremental_db/compiled_partitions/lcd.root_partition.map.kpt
lcd/incremental_db/compiled_partitions
lcd/incremental_db/README
lcd/incremental_db
lcd/lcd.asm.rpt
lcd/lcd.cdf
lcd/lcd.done
lcd/lcd.eda.rpt
lcd/lcd.fit.rpt
lcd/lcd.fit.smsg
lcd/lcd.fit.summary
lcd/lcd.flow.rpt
lcd/lcd.map.rpt
lcd/lcd.map.summary
lcd/lcd.pin
lcd/lcd.qpf
lcd/lcd.qsf
lcd/lcd.sof
lcd/lcd.sta.rpt
lcd/lcd.sta.summary
lcd/lcd.v
lcd/lcd.v.bak
lcd/lcd_nativelink_simulation.rpt
lcd/lcd_tb.v
lcd/lcd_tb.v.bak
lcd/simulation/modelsim/lcd.sft
lcd/simulation/modelsim/lcd.vo
lcd/simulation/modelsim/lcd_8_1200mv_0c_slow.vo
lcd/simulation/modelsim/lcd_8_1200mv_0c_v_slow.sdo
lcd/simulation/modelsim/lcd_8_1200mv_85c_slow.vo
lcd/simulation/modelsim/lcd_8_1200mv_85c_v_slow.sdo
lcd/simulation/modelsim/lcd_min_1200mv_0c_fast.vo
lcd/simulation/modelsim/lcd_min_1200mv_0c_v_fast.sdo
lcd/simulation/modelsim/lcd_modelsim.xrf
lcd/simulation/modelsim/lcd_run_msim_rtl_verilog.do
lcd/simulation/modelsim/lcd_run_msim_rtl_verilog.do.bak
lcd/simulation/modelsim/lcd_run_msim_rtl_verilog.do.bak1
lcd/simulation/modelsim/lcd_v.sdo
lcd/simulation/modelsim/modelsim.ini
lcd/simulation/modelsim/msim_transcript
lcd/simulation/modelsim/rtl_work/lcd/verilog.prw
lcd/simulation/modelsim/rtl_work/lcd/verilog.psm
lcd/simulation/modelsim/rtl_work/lcd/_primary.dat
lcd/simulation/modelsim/rtl_work/lcd/_primary.dbs
lcd/simulation/modelsim/rtl_work/lcd/_primary.vhd
lcd/simulation/modelsim/rtl_work/lcd
lcd/simulation/modelsim/rtl_work/lcd_tb/verilog.prw
lcd/simulation/modelsim/rtl_work/lcd_tb/verilog.psm
lcd/simulation/modelsim/rtl_work/lcd_tb/_primary.dat
lcd/simulation/modelsim/rtl_work/lcd_tb/_primary.dbs
lcd/simulation/modelsim/rtl_work/lcd_tb/_primary.vhd
lcd/simulation/modelsim/rtl_work/lcd_tb
lcd/simulation/modelsim/rtl_work/_info
lcd/simulation/modelsim/rtl_work/_temp
lcd/simulation/modelsim/rtl_work/_vmake
lcd/simulation/modelsim/rtl_work
lcd/simulation/modelsim/vsim.wlf
lcd/simulation/modelsim
lcd/simulation
lcd
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