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文件名称:MIPS

  • 所属分类：
    ARM-PowerPC-ColdFire-MIPS
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-03-16
  • 文件大小：
    5.48mb
  • 已下载：
    0次
  • 提 供 者：
    黄****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

简单的MIPS流水线实现，无相关处理。实现R指令，J指令或者I指令。-Simple MIPS pipelined related processing. To achieve the R command, directive, or I instruction.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CPU/ALUControl.v
CPU/Control.v
CPU/Control.v.bak
CPU/CPU.jdi
CPU/CPU.qpf
CPU/CPU.qsf
CPU/CPU.qws
CPU/CPU.v
CPU/CPU.v.bak
CPU/CPU_nativelink_simulation.rpt
CPU/db/CPU.(0).cnf.cdb
CPU/db/CPU.(0).cnf.hdb
CPU/db/CPU.(1).cnf.cdb
CPU/db/CPU.(1).cnf.hdb
CPU/db/CPU.(2).cnf.cdb
CPU/db/CPU.(2).cnf.hdb
CPU/db/CPU.(3).cnf.cdb
CPU/db/CPU.(3).cnf.hdb
CPU/db/CPU.(4).cnf.cdb
CPU/db/CPU.(4).cnf.hdb
CPU/db/CPU.(5).cnf.cdb
CPU/db/CPU.(5).cnf.hdb
CPU/db/CPU.(6).cnf.cdb
CPU/db/CPU.(6).cnf.hdb
CPU/db/CPU.asm.qmsg
CPU/db/CPU.asm.rdb
CPU/db/CPU.asm_labs.ddb
CPU/db/CPU.cbx.xml
CPU/db/CPU.cmp.bpm
CPU/db/CPU.cmp.cdb
CPU/db/CPU.cmp.hdb
CPU/db/CPU.cmp.idb
CPU/db/CPU.cmp.kpt
CPU/db/CPU.cmp.logdb
CPU/db/CPU.cmp.rdb
CPU/db/CPU.cmp_merge.kpt
CPU/db/CPU.db_info
CPU/db/CPU.eda.qmsg
CPU/db/CPU.fit.qmsg
CPU/db/CPU.hier_info
CPU/db/CPU.hif
CPU/db/CPU.ipinfo
CPU/db/CPU.lpc.html
CPU/db/CPU.lpc.rdb
CPU/db/CPU.lpc.txt
CPU/db/CPU.map.bpm
CPU/db/CPU.map.cdb
CPU/db/CPU.map.hdb
CPU/db/CPU.map.kpt
CPU/db/CPU.map.logdb
CPU/db/CPU.map.qmsg
CPU/db/CPU.map.rdb
CPU/db/CPU.map_bb.cdb
CPU/db/CPU.map_bb.hdb
CPU/db/CPU.map_bb.logdb
CPU/db/CPU.pre_map.cdb
CPU/db/CPU.pre_map.hdb
CPU/db/CPU.qns
CPU/db/CPU.ram0_RegFile_be88a862.hdl.mif
CPU/db/CPU.root_partition.map.reg_db.cdb
CPU/db/CPU.routing.rdb
CPU/db/CPU.rtlv.hdb
CPU/db/CPU.rtlv_sg.cdb
CPU/db/CPU.rtlv_sg_swap.cdb
CPU/db/CPU.sas
CPU/db/CPU.sgdiff.cdb
CPU/db/CPU.sgdiff.hdb
CPU/db/CPU.sld_design_entry.sci
CPU/db/CPU.sld_design_entry_dsc.sci
CPU/db/CPU.smart_action.txt
CPU/db/CPU.sta.qmsg
CPU/db/CPU.sta.rdb
CPU/db/CPU.sta_cmp.6_slow_1200mv_85c.tdb
CPU/db/CPU.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
CPU/db/CPU.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
CPU/db/CPU.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
CPU/db/CPU.syn_hier_info
CPU/db/CPU.tiscmp.fast_1200mv_0c.ddb
CPU/db/CPU.tiscmp.slow_1200mv_0c.ddb
CPU/db/CPU.tiscmp.slow_1200mv_85c.ddb
CPU/db/CPU.tis_db_list.ddb
CPU/db/CPU.tmw_info
CPU/db/CPU.vpr.ammdb
CPU/db/logic_util_heursitic.dat
CPU/db/prev_cmp_CPU.qmsg
CPU/DMemory.v
CPU/DMemory.v.bak
CPU/IMemory.v
CPU/IMemory.v.bak
CPU/incremental_db/compiled_partitions/CPU.db_info
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.ammdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.cdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.dfp
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.hdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.kpt
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.logdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.rcfdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.cdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.dpi
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.cdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.hb_info
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.hdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.sig
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hdb
CPU/incremental_db/compiled_partitions/CPU.root_partition.map.kpt
CPU/incremental_db/README
CPU/MIPSALU.v
CPU/output_files/CPU.asm.rpt
CPU/output_files/CPU.done
CPU/output_files/CPU.eda.rpt
CPU/output_files/CPU.fit.rpt
CPU/output_files/CPU.fit.smsg
CPU/output_files/CPU.fit.summary
CPU/output_files/CPU.flow.rpt
CPU/output_files/CPU.jdi
CPU/output_files/CPU.map.rpt
CPU/output_files/CPU.map.smsg
CPU/output_files/CPU.map.summary
CPU/output_files/CPU.pin
CPU/output_files/CPU.sof
CPU/output_files/CPU.sta.rpt
CPU/output_files/CPU.sta.summary
CPU/RegFile.v
CPU/RegFile.v.bak
CPU/simulation/modelsim/CPU.sft
CPU/simulation/modelsim/CPU.vo
CPU/simulation/modelsim/CPU_6_1200mv_0c_slow.vo
CPU/simulation/modelsim/CPU_6_1200mv_0c_v_slow.sdo
CPU/simulation/modelsim/CPU_6_1200mv_85c_slow.vo
CPU/simulation/modelsim/CPU_6_1200mv_85c_v_slow.sdo
CPU/simulation/modelsim/CPU_min_1200mv_0c_fast.vo
CPU/simulation/modelsim/CPU_min_1200mv_0c_v_fast.sdo
CPU/simulation/modelsim/CPU_modelsim.xrf
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak1
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak10
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak11
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak2
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak3
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak4
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak5
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak6
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak7
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak8
CPU/simulation/modelsim/CPU_run_msim_rtl_verilog.do.bak9
CPU/simulation/modelsim/CPU_v.sdo
CPU/simulation/modelsim/modelsim.ini
CPU/simulation/modelsim/msim_transcript
CPU/simulation/modelsim/rtl_work/@a@l@u@control/verilog.prw
CPU/simulation/modelsim/rtl_work/@a@l@u@control/verilog.psm
CPU/simulation/modelsim/rtl_work/@a@l@u@control/_primary.dat
CPU/simulation/modelsim/rtl_work/

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