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文件名称:SinPout

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-03-16
  • 文件大小：
    232.03kb
  • 已下载：
    0次
  • 提 供 者：
    wic****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

FPGA设计中涉及到的速度与面积互换技巧，本工程的代码用Verilog编写，实现功能串行输入并行输出-It comes to speed and area interchangeable FPGA design skills, the project code written in Verilog function serial input parallel output
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SinPout/db/logic_util_heursitic.dat
SinPout/db/prev_cmp_sp.qmsg
SinPout/db/sp.map_bb.logdb
SinPout/db/sp_top.(0).cnf.cdb
SinPout/db/sp_top.(0).cnf.hdb
SinPout/db/sp_top.(1).cnf.cdb
SinPout/db/sp_top.(1).cnf.hdb
SinPout/db/sp_top.(2).cnf.cdb
SinPout/db/sp_top.(2).cnf.hdb
SinPout/db/sp_top.amm.cdb
SinPout/db/sp_top.asm.qmsg
SinPout/db/sp_top.asm.rdb
SinPout/db/sp_top.cbx.xml
SinPout/db/sp_top.cmp.bpm
SinPout/db/sp_top.cmp.cbp
SinPout/db/sp_top.cmp.cdb
SinPout/db/sp_top.cmp.hdb
SinPout/db/sp_top.cmp.kpt
SinPout/db/sp_top.cmp.logdb
SinPout/db/sp_top.cmp.rdb
SinPout/db/sp_top.cmp.tdb
SinPout/db/sp_top.cmp0.ddb
SinPout/db/sp_top.cmp_merge.kpt
SinPout/db/sp_top.db_info
SinPout/db/sp_top.eda.qmsg
SinPout/db/sp_top.fit.qmsg
SinPout/db/sp_top.hier_info
SinPout/db/sp_top.hif
SinPout/db/sp_top.idb.cdb
SinPout/db/sp_top.lpc.html
SinPout/db/sp_top.lpc.rdb
SinPout/db/sp_top.lpc.txt
SinPout/db/sp_top.map.bpm
SinPout/db/sp_top.map.cbp
SinPout/db/sp_top.map.cdb
SinPout/db/sp_top.map.hdb
SinPout/db/sp_top.map.kpt
SinPout/db/sp_top.map.qmsg
SinPout/db/sp_top.map_bb.cdb
SinPout/db/sp_top.map_bb.hdb
SinPout/db/sp_top.pre_map.cdb
SinPout/db/sp_top.pre_map.hdb
SinPout/db/sp_top.rtlv.hdb
SinPout/db/sp_top.rtlv_sg.cdb
SinPout/db/sp_top.rtlv_sg_swap.cdb
SinPout/db/sp_top.sgdiff.cdb
SinPout/db/sp_top.sgdiff.hdb
SinPout/db/sp_top.sld_design_entry.sci
SinPout/db/sp_top.sld_design_entry_dsc.sci
SinPout/db/sp_top.smart_action.txt
SinPout/db/sp_top.syn_hier_info
SinPout/db/sp_top.tan.qmsg
SinPout/db/sp_top.tis_db_list.ddb
SinPout/db/sp_top.tmw_info
SinPout/incremental_db/compiled_partitions/sp_top.db_info
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.cmp.cdb
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.cmp.dfp
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.cmp.hdb
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.cmp.kpt
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.cmp.logdb
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.cmp.rcfdb
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.cmp.re.rcfdb
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.map.cdb
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.map.dpi
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.map.hdb
SinPout/incremental_db/compiled_partitions/sp_top.root_partition.map.kpt
SinPout/incremental_db/README
SinPout/parallel_out.v
SinPout/parallel_out.v.bak
SinPout/series_in.v
SinPout/series_in.v.bak
SinPout/simulation/modelsim/modelsim.ini
SinPout/simulation/modelsim/msim_transcript
SinPout/simulation/modelsim/rtl_work/parallel_out/verilog.prw
SinPout/simulation/modelsim/rtl_work/parallel_out/verilog.psm
SinPout/simulation/modelsim/rtl_work/parallel_out/_primary.dat
SinPout/simulation/modelsim/rtl_work/parallel_out/_primary.dbs
SinPout/simulation/modelsim/rtl_work/parallel_out/_primary.vhd
SinPout/simulation/modelsim/rtl_work/series_in/verilog.prw
SinPout/simulation/modelsim/rtl_work/series_in/verilog.psm
SinPout/simulation/modelsim/rtl_work/series_in/_primary.dat
SinPout/simulation/modelsim/rtl_work/series_in/_primary.dbs
SinPout/simulation/modelsim/rtl_work/series_in/_primary.vhd
SinPout/simulation/modelsim/rtl_work/sp_top/verilog.prw
SinPout/simulation/modelsim/rtl_work/sp_top/verilog.psm
SinPout/simulation/modelsim/rtl_work/sp_top/_primary.dat
SinPout/simulation/modelsim/rtl_work/sp_top/_primary.dbs
SinPout/simulation/modelsim/rtl_work/sp_top/_primary.vhd
SinPout/simulation/modelsim/rtl_work/sp_top_vlg_tst/verilog.prw
SinPout/simulation/modelsim/rtl_work/sp_top_vlg_tst/verilog.psm
SinPout/simulation/modelsim/rtl_work/sp_top_vlg_tst/_primary.dat
SinPout/simulation/modelsim/rtl_work/sp_top_vlg_tst/_primary.dbs
SinPout/simulation/modelsim/rtl_work/sp_top_vlg_tst/_primary.vhd
SinPout/simulation/modelsim/rtl_work/_info
SinPout/simulation/modelsim/rtl_work/_vmake
SinPout/simulation/modelsim/sp_top.sft
SinPout/simulation/modelsim/sp_top.vo
SinPout/simulation/modelsim/sp_top.vt
SinPout/simulation/modelsim/sp_top.vt.bak
SinPout/simulation/modelsim/sp_top_modelsim.xrf
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak1
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak10
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak11
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak2
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak3
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak4
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak5
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak6
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak7
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak8
SinPout/simulation/modelsim/sp_top_run_msim_rtl_verilog.do.bak9
SinPout/simulation/modelsim/sp_top_v.sdo
SinPout/simulation/modelsim/vsim.wlf
SinPout/sp.qpf
SinPout/sp_top.asm.rpt
SinPout/sp_top.done
SinPout/sp_top.eda.rpt
Sin

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