文件名称:RD1088_rev01.2
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- 上传时间:2013-03-16
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文件大小:1.34mb
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已下载:1次
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介绍说明--下载内容来自于网络,使用问题请自行百度
FPGA或CPLD读取SD卡的IP核,基于wishbone接口,支持SDHC2.0,包含了使用说明,为Verilog语言编写-FPGA or CPLD reads the SD card IP core, based on the wishbone interface, support SDHC2.0, contains instructions for the Verilog language
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下载文件列表
RD1088_rev01.2/
RD1088_rev01.2/Docs/
RD1088_rev01.2/Docs/rd1088.pdf
RD1088_rev01.2/Docs/rd1088_readme.txt
RD1088_rev01.2/Project/
RD1088_rev01.2/Project/sd_card_controller.lpf
RD1088_rev01.2/Project/SD_controller_top_tb.udo_example
RD1088_rev01.2/simulation/
RD1088_rev01.2/simulation/verilog/
RD1088_rev01.2/simulation/verilog/rtl_verilog.do
RD1088_rev01.2/simulation/verilog/timing_verilog.do
RD1088_rev01.2/Source/
RD1088_rev01.2/Source/verilog/
RD1088_rev01.2/Source/verilog/SD_Bd.v
RD1088_rev01.2/Source/verilog/SD_cmd_master.v
RD1088_rev01.2/Source/verilog/SD_cmd_serial_host.v
RD1088_rev01.2/Source/verilog/SD_controller_top.v
RD1088_rev01.2/Source/verilog/SD_controller_wb.v
RD1088_rev01.2/Source/verilog/SD_crc_16.v
RD1088_rev01.2/Source/verilog/SD_crc_7.v
RD1088_rev01.2/Source/verilog/SD_data_host.v
RD1088_rev01.2/Source/verilog/SD_data_master.v
RD1088_rev01.2/Source/verilog/SD_defines.v
RD1088_rev01.2/Source/verilog/SD_FIFO_RX_Filler.v
RD1088_rev01.2/Source/verilog/SD_FIFO_TX_Filler.v
RD1088_rev01.2/Source/verilog/smii_rx_fifo.v
RD1088_rev01.2/Source/verilog/smii_tx_fifo.v
RD1088_rev01.2/Testbench/
RD1088_rev01.2/Testbench/verilog/
RD1088_rev01.2/Testbench/verilog/FLASH.txt
RD1088_rev01.2/Testbench/verilog/log/
RD1088_rev01.2/Testbench/verilog/log/eth_tb_host.log
RD1088_rev01.2/Testbench/verilog/log/eth_tb_phy.log
RD1088_rev01.2/Testbench/verilog/log/eth_tb_wb_m_mon.log
RD1088_rev01.2/Testbench/verilog/log/eth_tb_wb_s_mon.log
RD1088_rev01.2/Testbench/verilog/log/sdc_tb.log
RD1088_rev01.2/Testbench/verilog/log/sd_model.log
RD1088_rev01.2/Testbench/verilog/log/sd_tb_memory.log
RD1088_rev01.2/Testbench/verilog/sdModel.v
RD1088_rev01.2/Testbench/verilog/SD_controller_top_tb.v
RD1088_rev01.2/Testbench/verilog/wb_bus_mon.v
RD1088_rev01.2/Testbench/verilog/wb_master32.v
RD1088_rev01.2/Testbench/verilog/wb_master_behavioral.v
RD1088_rev01.2/Testbench/verilog/wb_memory.txt
RD1088_rev01.2/Testbench/verilog/wb_model_defines.v
RD1088_rev01.2/Testbench/verilog/wb_slave_behavioral.v
RD1088_rev01.2/Docs/
RD1088_rev01.2/Docs/rd1088.pdf
RD1088_rev01.2/Docs/rd1088_readme.txt
RD1088_rev01.2/Project/
RD1088_rev01.2/Project/sd_card_controller.lpf
RD1088_rev01.2/Project/SD_controller_top_tb.udo_example
RD1088_rev01.2/simulation/
RD1088_rev01.2/simulation/verilog/
RD1088_rev01.2/simulation/verilog/rtl_verilog.do
RD1088_rev01.2/simulation/verilog/timing_verilog.do
RD1088_rev01.2/Source/
RD1088_rev01.2/Source/verilog/
RD1088_rev01.2/Source/verilog/SD_Bd.v
RD1088_rev01.2/Source/verilog/SD_cmd_master.v
RD1088_rev01.2/Source/verilog/SD_cmd_serial_host.v
RD1088_rev01.2/Source/verilog/SD_controller_top.v
RD1088_rev01.2/Source/verilog/SD_controller_wb.v
RD1088_rev01.2/Source/verilog/SD_crc_16.v
RD1088_rev01.2/Source/verilog/SD_crc_7.v
RD1088_rev01.2/Source/verilog/SD_data_host.v
RD1088_rev01.2/Source/verilog/SD_data_master.v
RD1088_rev01.2/Source/verilog/SD_defines.v
RD1088_rev01.2/Source/verilog/SD_FIFO_RX_Filler.v
RD1088_rev01.2/Source/verilog/SD_FIFO_TX_Filler.v
RD1088_rev01.2/Source/verilog/smii_rx_fifo.v
RD1088_rev01.2/Source/verilog/smii_tx_fifo.v
RD1088_rev01.2/Testbench/
RD1088_rev01.2/Testbench/verilog/
RD1088_rev01.2/Testbench/verilog/FLASH.txt
RD1088_rev01.2/Testbench/verilog/log/
RD1088_rev01.2/Testbench/verilog/log/eth_tb_host.log
RD1088_rev01.2/Testbench/verilog/log/eth_tb_phy.log
RD1088_rev01.2/Testbench/verilog/log/eth_tb_wb_m_mon.log
RD1088_rev01.2/Testbench/verilog/log/eth_tb_wb_s_mon.log
RD1088_rev01.2/Testbench/verilog/log/sdc_tb.log
RD1088_rev01.2/Testbench/verilog/log/sd_model.log
RD1088_rev01.2/Testbench/verilog/log/sd_tb_memory.log
RD1088_rev01.2/Testbench/verilog/sdModel.v
RD1088_rev01.2/Testbench/verilog/SD_controller_top_tb.v
RD1088_rev01.2/Testbench/verilog/wb_bus_mon.v
RD1088_rev01.2/Testbench/verilog/wb_master32.v
RD1088_rev01.2/Testbench/verilog/wb_master_behavioral.v
RD1088_rev01.2/Testbench/verilog/wb_memory.txt
RD1088_rev01.2/Testbench/verilog/wb_model_defines.v
RD1088_rev01.2/Testbench/verilog/wb_slave_behavioral.v
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