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文件名称:openmsp430_latest.tar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2013-03-16
  • 文件大小：
    36.25mb
  • 已下载：
    0次
  • 提 供 者：
    k***
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

The openMSP430 is a 16-bit microcontroller core compatible with TI s MSP430 family

(note that the extended version of the architecture, the MSP430X, isn t supported by this

IP). It is based on a Von Neumann architecture, with a single address space for

instructions and data-The openMSP430 is a 16-bit microcontroller core compatible with TI s MSP430 family

(note that the extended version of the architecture, the MSP430X, isn t supported by this

IP).　 It　 is　 based　 on　 a　 Von　 Neumann　 architecture,　 with　 a　 single　 address　 space　 for

instructions and data
(系统自动生成,下载前可以参看下载内容)

下载文件列表

openmsp430/
openmsp430/tags/
openmsp430/branches/
openmsp430/trunk/
openmsp430/trunk/ChangeLog_core.txt
openmsp430/trunk/fpga/
openmsp430/trunk/fpga/xilinx_diligent_s3board/
openmsp430/trunk/fpga/xilinx_diligent_s3board/doc/
openmsp430/trunk/fpga/xilinx_diligent_s3board/doc/msp430f1121a.pdf
openmsp430/trunk/fpga/xilinx_diligent_s3board/doc/xapp462.pdf
openmsp430/trunk/fpga/xilinx_diligent_s3board/doc/board_user_guide.pdf
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/3_program_fpga.sh
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/openMSP430_fpga.ucf
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/memory.bmm
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/impact_program_fpga.batch
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/impact_generate_prom_file.batch
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/openMSP430_fpga.prj
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/xst_verilog.opt
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/ihex2mem.tcl
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/2_generate_prom_file.sh
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/ta_uart.bit
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/README.jpg
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/leds.mcs
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/openMSP430_fpga.bit
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/hw_uart.bit
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/hw_uart.mcs
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/openMSP430_fpga.mcs
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/leds.bit
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/ta_uart.mcs
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/win_1_initialize_pmem.bat
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/1_initialize_pmem.sh
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/win_0_create_bitstream.bat
openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/0_create_bitstream.sh
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/run
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/run_disassemble
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/omsp_config.sh
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/rtlsim.sh
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/ta_uart.v
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/hw_uart.v
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/leds.v
openmsp430/trunk/fpga/xilinx_diligent_s3board/README
openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/
openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/
openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/timescale.v
openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v
openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v
openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/glbl.v
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/omsp_system.h
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/hardware.h
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/main.c
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/makefile
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/linker.x
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/omsp_uart.h
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/ta_uart/
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/ta_uart/fll.s
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/ta_uart/README.txt
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/ta_uart/fll.h
openmsp430/trunk/fpga/xilinx_diligent_s3board/software/ta_uart/hardware.h
openmsp430/trunk/fpga/xilinx_

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