文件名称:RISC-CPU
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- 上传时间:2013-03-28
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文件大小:3.14mb
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精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写 含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
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下载文件列表
RISC-CPU/.nclaunch.dd
RISC-CPU/.nclaunch.dd.bak
RISC-CPU/.simvision/dbrowser-bookmarks
RISC-CPU/.simvision/schematic-bookmarks
RISC-CPU/.simvision/source-bookmarks
RISC-CPU/accum.v
RISC-CPU/addr.v
RISC-CPU/alu_out.ddc
RISC-CPU/alu_out.v
RISC-CPU/cds.lib
RISC-CPU/choose.v
RISC-CPU/clkgen.v
RISC-CPU/command.log
RISC-CPU/counter.v
RISC-CPU/cpu.txt
RISC-CPU/cpu.v
RISC-CPU/datactl.v
RISC-CPU/data_choose.v
RISC-CPU/default.svf
RISC-CPU/filenames.log
RISC-CPU/hdl.var
RISC-CPU/INCA_libs/worklib/.cdsvmod
RISC-CPU/INCA_libs/worklib/.inca.db.179.lnx86
RISC-CPU/INCA_libs/worklib/inca.lnx86.179.pak
RISC-CPU/machine.v
RISC-CPU/ncelab.log
RISC-CPU/nclaunch.key
RISC-CPU/ncsim.key
RISC-CPU/ncsim.log
RISC-CPU/ncvlog.log
RISC-CPU/ram.v
RISC-CPU/register.v
RISC-CPU/RSUC.v
RISC-CPU/tb.v
RISC-CPU/typical.db
RISC-CPU/umc18/.cdsvmod
RISC-CPU/umc18/.inca.db.179.lnx86
RISC-CPU/umc18/inca.lnx86.179.pak
RISC-CPU/umc18.sdb
RISC-CPU/umc18.v
RISC-CPU/waves.shm/waves-1.trn
RISC-CPU/waves.shm/waves-10.trn
RISC-CPU/waves.shm/waves-11.trn
RISC-CPU/waves.shm/waves-12.trn
RISC-CPU/waves.shm/waves-13.trn
RISC-CPU/waves.shm/waves-2.trn
RISC-CPU/waves.shm/waves-3.trn
RISC-CPU/waves.shm/waves-4.trn
RISC-CPU/waves.shm/waves-5.trn
RISC-CPU/waves.shm/waves-6.trn
RISC-CPU/waves.shm/waves-7.trn
RISC-CPU/waves.shm/waves-8.trn
RISC-CPU/waves.shm/waves-9.trn
RISC-CPU/waves.shm/waves.dsn
RISC-CPU/waves.shm/waves.trn
RISC-CPU/INCA_libs/worklib
RISC-CPU/.simvision
RISC-CPU/INCA_libs
RISC-CPU/umc18
RISC-CPU/waves.shm
RISC-CPU
RISC-CPU/.nclaunch.dd.bak
RISC-CPU/.simvision/dbrowser-bookmarks
RISC-CPU/.simvision/schematic-bookmarks
RISC-CPU/.simvision/source-bookmarks
RISC-CPU/accum.v
RISC-CPU/addr.v
RISC-CPU/alu_out.ddc
RISC-CPU/alu_out.v
RISC-CPU/cds.lib
RISC-CPU/choose.v
RISC-CPU/clkgen.v
RISC-CPU/command.log
RISC-CPU/counter.v
RISC-CPU/cpu.txt
RISC-CPU/cpu.v
RISC-CPU/datactl.v
RISC-CPU/data_choose.v
RISC-CPU/default.svf
RISC-CPU/filenames.log
RISC-CPU/hdl.var
RISC-CPU/INCA_libs/worklib/.cdsvmod
RISC-CPU/INCA_libs/worklib/.inca.db.179.lnx86
RISC-CPU/INCA_libs/worklib/inca.lnx86.179.pak
RISC-CPU/machine.v
RISC-CPU/ncelab.log
RISC-CPU/nclaunch.key
RISC-CPU/ncsim.key
RISC-CPU/ncsim.log
RISC-CPU/ncvlog.log
RISC-CPU/ram.v
RISC-CPU/register.v
RISC-CPU/RSUC.v
RISC-CPU/tb.v
RISC-CPU/typical.db
RISC-CPU/umc18/.cdsvmod
RISC-CPU/umc18/.inca.db.179.lnx86
RISC-CPU/umc18/inca.lnx86.179.pak
RISC-CPU/umc18.sdb
RISC-CPU/umc18.v
RISC-CPU/waves.shm/waves-1.trn
RISC-CPU/waves.shm/waves-10.trn
RISC-CPU/waves.shm/waves-11.trn
RISC-CPU/waves.shm/waves-12.trn
RISC-CPU/waves.shm/waves-13.trn
RISC-CPU/waves.shm/waves-2.trn
RISC-CPU/waves.shm/waves-3.trn
RISC-CPU/waves.shm/waves-4.trn
RISC-CPU/waves.shm/waves-5.trn
RISC-CPU/waves.shm/waves-6.trn
RISC-CPU/waves.shm/waves-7.trn
RISC-CPU/waves.shm/waves-8.trn
RISC-CPU/waves.shm/waves-9.trn
RISC-CPU/waves.shm/waves.dsn
RISC-CPU/waves.shm/waves.trn
RISC-CPU/INCA_libs/worklib
RISC-CPU/.simvision
RISC-CPU/INCA_libs
RISC-CPU/umc18
RISC-CPU/waves.shm
RISC-CPU
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