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文件名称:dpsk_3rd

  • 所属分类：
    VHDL编程
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-04-02
  • 文件大小：
    246.64kb
  • 已下载：
    1次
  • 提 供 者：
    韩****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

2DPSK调制与解调。学生实验使用，包括信号源模块、时钟源生成模块、信号调制模块，信号解调模块。

其中包含了边沿触发下的阻塞语句。

编译环境：Q2 11.0，编译语言：verilog，仿真软件：moelsim altera -2DPSK modulation and demodulation. The student experiments, including the source module clock source generation module, signal modulation module, signal demodulation module. Contains a the blocking statement under the edge-triggered. Compilation environment: Q2 11.0, compiled language: verilog, simulation software: moelsim altera
(系统自动生成,下载前可以参看下载内容)

下载文件列表

dpsk_3rd/clk_std.v
dpsk_3rd/clk_std.v.bak
dpsk_3rd/db/dpsk_3rd.(0).cnf.cdb
dpsk_3rd/db/dpsk_3rd.(0).cnf.hdb
dpsk_3rd/db/dpsk_3rd.(1).cnf.cdb
dpsk_3rd/db/dpsk_3rd.(1).cnf.hdb
dpsk_3rd/db/dpsk_3rd.(2).cnf.cdb
dpsk_3rd/db/dpsk_3rd.(2).cnf.hdb
dpsk_3rd/db/dpsk_3rd.(3).cnf.cdb
dpsk_3rd/db/dpsk_3rd.(3).cnf.hdb
dpsk_3rd/db/dpsk_3rd.(4).cnf.cdb
dpsk_3rd/db/dpsk_3rd.(4).cnf.hdb
dpsk_3rd/db/dpsk_3rd.amm.cdb
dpsk_3rd/db/dpsk_3rd.asm.qmsg
dpsk_3rd/db/dpsk_3rd.asm.rdb
dpsk_3rd/db/dpsk_3rd.asm_labs.ddb
dpsk_3rd/db/dpsk_3rd.cbx.xml
dpsk_3rd/db/dpsk_3rd.cmp.cdb
dpsk_3rd/db/dpsk_3rd.cmp.hdb
dpsk_3rd/db/dpsk_3rd.cmp.kpt
dpsk_3rd/db/dpsk_3rd.cmp.logdb
dpsk_3rd/db/dpsk_3rd.cmp.rdb
dpsk_3rd/db/dpsk_3rd.cmp0.ddb
dpsk_3rd/db/dpsk_3rd.db_info
dpsk_3rd/db/dpsk_3rd.eda.qmsg
dpsk_3rd/db/dpsk_3rd.fit.qmsg
dpsk_3rd/db/dpsk_3rd.hier_info
dpsk_3rd/db/dpsk_3rd.hif
dpsk_3rd/db/dpsk_3rd.idb.cdb
dpsk_3rd/db/dpsk_3rd.lpc.html
dpsk_3rd/db/dpsk_3rd.lpc.rdb
dpsk_3rd/db/dpsk_3rd.lpc.txt
dpsk_3rd/db/dpsk_3rd.map.cdb
dpsk_3rd/db/dpsk_3rd.map.hdb
dpsk_3rd/db/dpsk_3rd.map.logdb
dpsk_3rd/db/dpsk_3rd.map.qmsg
dpsk_3rd/db/dpsk_3rd.pre_map.cdb
dpsk_3rd/db/dpsk_3rd.pre_map.hdb
dpsk_3rd/db/dpsk_3rd.rtlv.hdb
dpsk_3rd/db/dpsk_3rd.rtlv_sg.cdb
dpsk_3rd/db/dpsk_3rd.rtlv_sg_swap.cdb
dpsk_3rd/db/dpsk_3rd.sgdiff.cdb
dpsk_3rd/db/dpsk_3rd.sgdiff.hdb
dpsk_3rd/db/dpsk_3rd.sld_design_entry.sci
dpsk_3rd/db/dpsk_3rd.sld_design_entry_dsc.sci
dpsk_3rd/db/dpsk_3rd.smart_action.txt
dpsk_3rd/db/dpsk_3rd.sta.qmsg
dpsk_3rd/db/dpsk_3rd.sta.rdb
dpsk_3rd/db/dpsk_3rd.sta_cmp.5_slow.tdb
dpsk_3rd/db/dpsk_3rd.syn_hier_info
dpsk_3rd/db/dpsk_3rd.tis_db_list.ddb
dpsk_3rd/db/dpsk_3rd.tmw_info
dpsk_3rd/db/logic_util_heursitic.dat
dpsk_3rd/db/prev_cmp_dpsk_3rd.qmsg
dpsk_3rd/dpsk_3rd.asm.rpt
dpsk_3rd/dpsk_3rd.done
dpsk_3rd/dpsk_3rd.eda.rpt
dpsk_3rd/dpsk_3rd.fit.rpt
dpsk_3rd/dpsk_3rd.fit.smsg
dpsk_3rd/dpsk_3rd.fit.summary
dpsk_3rd/dpsk_3rd.flow.rpt
dpsk_3rd/dpsk_3rd.map.rpt
dpsk_3rd/dpsk_3rd.map.smsg
dpsk_3rd/dpsk_3rd.map.summary
dpsk_3rd/dpsk_3rd.pin
dpsk_3rd/dpsk_3rd.pof
dpsk_3rd/dpsk_3rd.qpf
dpsk_3rd/dpsk_3rd.qsf
dpsk_3rd/dpsk_3rd.sta.rpt
dpsk_3rd/dpsk_3rd.sta.summary
dpsk_3rd/dpsk_3rd.v
dpsk_3rd/dpsk_3rd.v.bak
dpsk_3rd/dpsk_3rd_nativelink_simulation.rpt
dpsk_3rd/incremental_db/compiled_partitions/dpsk_3rd.db_info
dpsk_3rd/incremental_db/compiled_partitions/dpsk_3rd.root_partition.map.kpt
dpsk_3rd/incremental_db/README
dpsk_3rd/re_dpsk_first.v
dpsk_3rd/re_dpsk_first.v.bak
dpsk_3rd/signal.v
dpsk_3rd/signal.v.bak
dpsk_3rd/simulation/modelsim/dpsk_3rd.sft
dpsk_3rd/simulation/modelsim/dpsk_3rd.vo
dpsk_3rd/simulation/modelsim/dpsk_3rd_modelsim.xrf
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak1
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak10
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak11
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak2
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak3
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak4
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak5
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak6
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak7
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak8
dpsk_3rd/simulation/modelsim/dpsk_3rd_run_msim_rtl_verilog.do.bak9
dpsk_3rd/simulation/modelsim/dpsk_3rd_v.sdo
dpsk_3rd/simulation/modelsim/modelsim.ini
dpsk_3rd/simulation/modelsim/msim_transcript
dpsk_3rd/simulation/modelsim/rtl_work/clk_std/verilog.prw
dpsk_3rd/simulation/modelsim/rtl_work/clk_std/verilog.psm
dpsk_3rd/simulation/modelsim/rtl_work/clk_std/_primary.dat
dpsk_3rd/simulation/modelsim/rtl_work/clk_std/_primary.dbs
dpsk_3rd/simulation/modelsim/rtl_work/clk_std/_primary.vhd
dpsk_3rd/simulation/modelsim/rtl_work/dpsk_3rd/verilog.prw
dpsk_3rd/simulation/modelsim/rtl_work/dpsk_3rd/verilog.psm
dpsk_3rd/simulation/modelsim/rtl_work/dpsk_3rd/_primary.dat
dpsk_3rd/simulation/modelsim/rtl_work/dpsk_3rd/_primary.dbs
dpsk_3rd/simulation/modelsim/rtl_work/dpsk_3rd/_primary.vhd
dpsk_3rd/simulation/modelsim/rtl_work/re_dpsk_first/verilog.prw
dpsk_3rd/simulation/modelsim/rtl_work/re_dpsk_first/verilog.psm
dpsk_3rd/simulation/modelsim/rtl_work/re_dpsk_first/_primary.dat
dpsk_3rd/simulation/modelsim/rtl_work/re_dpsk_first/_primary.dbs
dpsk_3rd/simulation/modelsim/rtl_work/re_dpsk_first/_primary.vhd
dpsk_3rd/simulation/modelsim/rtl_work/signal/verilog.prw
dpsk_3rd/simulation/modelsim/rtl_work/signal/verilog.psm
dpsk_3rd/simulation/modelsim/rtl_work/signal/_primary.dat
dpsk_3rd/simulation/modelsim/rtl_work/signal/_primary.dbs
dpsk_3rd/simulation/modelsim/rtl_work/signal/_primary.vhd
dpsk_3rd/simulation/modelsim/rtl_work/top/verilog.prw
dpsk_3rd/simulation/modelsim/rtl_work/top/verilog.psm
dpsk_3rd/simulation/modelsim/rtl_work/top/_primary.dat
dpsk_3rd/simulation/modelsim/rtl_work/top/_primary.dbs
dpsk_3rd/simulation/modelsim/rtl_work/top/_primary.vhd
dpsk_3rd/simulation/modelsim/rtl_work/to

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