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文件名称:SPI_fpga_w_r_sigle

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-04-08
  • 文件大小：
    2.53mb
  • 已下载：
    0次
  • 提 供 者：
    飞****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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verilog fpga spi slave 收发测试 有简单的协议 modelsim仿真通过 -simple protocol modelsim verilog fpga spi slave transceiver test simulation by
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SPI_fpga_w_r_sigle/
SPI_fpga_w_r_sigle/SPI1.archive.rpt
SPI_fpga_w_r_sigle/SPI1.done
SPI_fpga_w_r_sigle/SPI1.eda.rpt
SPI_fpga_w_r_sigle/SPI1.flow.rpt
SPI_fpga_w_r_sigle/SPI1.map.rpt
SPI_fpga_w_r_sigle/SPI1.map.smsg
SPI_fpga_w_r_sigle/SPI1.map.summary
SPI_fpga_w_r_sigle/SPI1.qpf
SPI_fpga_w_r_sigle/SPI1.qsf
SPI_fpga_w_r_sigle/SPI1.qws
SPI_fpga_w_r_sigle/SPI1.v
SPI_fpga_w_r_sigle/SPI1.v.bak
SPI_fpga_w_r_sigle/SPI1_nativelink_simulation.rpt
SPI_fpga_w_r_sigle/SPI_W_R.qar
SPI_fpga_w_r_sigle/SPI_W_R.qarlog
SPI_fpga_w_r_sigle/__SPI1.auto.qarlog
SPI_fpga_w_r_sigle/db/
SPI_fpga_w_r_sigle/db/SPI1.(0).cnf.cdb
SPI_fpga_w_r_sigle/db/SPI1.(0).cnf.hdb
SPI_fpga_w_r_sigle/db/SPI1.archive.qmsg
SPI_fpga_w_r_sigle/db/SPI1.archiver.cache
SPI_fpga_w_r_sigle/db/SPI1.cbx.xml
SPI_fpga_w_r_sigle/db/SPI1.cmp.rdb
SPI_fpga_w_r_sigle/db/SPI1.cmp_merge.kpt
SPI_fpga_w_r_sigle/db/SPI1.db_info
SPI_fpga_w_r_sigle/db/SPI1.eda.qmsg
SPI_fpga_w_r_sigle/db/SPI1.hier_info
SPI_fpga_w_r_sigle/db/SPI1.hif
SPI_fpga_w_r_sigle/db/SPI1.lpc.html
SPI_fpga_w_r_sigle/db/SPI1.lpc.rdb
SPI_fpga_w_r_sigle/db/SPI1.lpc.txt
SPI_fpga_w_r_sigle/db/SPI1.map.bpm
SPI_fpga_w_r_sigle/db/SPI1.map.cdb
SPI_fpga_w_r_sigle/db/SPI1.map.hdb
SPI_fpga_w_r_sigle/db/SPI1.map.kpt
SPI_fpga_w_r_sigle/db/SPI1.map.logdb
SPI_fpga_w_r_sigle/db/SPI1.map.qmsg
SPI_fpga_w_r_sigle/db/SPI1.map.rdb
SPI_fpga_w_r_sigle/db/SPI1.map_bb.cdb
SPI_fpga_w_r_sigle/db/SPI1.map_bb.hdb
SPI_fpga_w_r_sigle/db/SPI1.map_bb.logdb
SPI_fpga_w_r_sigle/db/SPI1.pre_map.cdb
SPI_fpga_w_r_sigle/db/SPI1.pre_map.hdb
SPI_fpga_w_r_sigle/db/SPI1.qpf
SPI_fpga_w_r_sigle/db/SPI1.root_partition.map.reg_db.cdb
SPI_fpga_w_r_sigle/db/SPI1.rtlv.hdb
SPI_fpga_w_r_sigle/db/SPI1.rtlv_sg.cdb
SPI_fpga_w_r_sigle/db/SPI1.rtlv_sg_swap.cdb
SPI_fpga_w_r_sigle/db/SPI1.sgdiff.cdb
SPI_fpga_w_r_sigle/db/SPI1.sgdiff.hdb
SPI_fpga_w_r_sigle/db/SPI1.sld_design_entry.sci
SPI_fpga_w_r_sigle/db/SPI1.sld_design_entry_dsc.sci
SPI_fpga_w_r_sigle/db/SPI1.smart_action.txt
SPI_fpga_w_r_sigle/db/SPI1.syn_hier_info
SPI_fpga_w_r_sigle/db/SPI1.tis_db_list.ddb
SPI_fpga_w_r_sigle/db/logic_util_heursitic.dat
SPI_fpga_w_r_sigle/db/prev_cmp_SPI1.qmsg
SPI_fpga_w_r_sigle/incremental_db/
SPI_fpga_w_r_sigle/incremental_db/README
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/SPI1.db_info
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/SPI1.root_partition.map.cdb
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/SPI1.root_partition.map.dpi
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/SPI1.root_partition.map.hbdb.cdb
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/SPI1.root_partition.map.hbdb.hb_info
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/SPI1.root_partition.map.hbdb.hdb
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/SPI1.root_partition.map.hbdb.sig
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/SPI1.root_partition.map.hdb
SPI_fpga_w_r_sigle/incremental_db/compiled_partitions/SPI1.root_partition.map.kpt
SPI_fpga_w_r_sigle/simulation/
SPI_fpga_w_r_sigle/simulation/modelsim/
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1.vt.bak
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak1
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak10
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak11
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak2
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak3
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak4
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak5
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak6
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak7
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak8
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_run_msim_rtl_verilog.do.bak9
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_vlg_tst.vt
SPI_fpga_w_r_sigle/simulation/modelsim/SPI1_vlg_tst.vt.bak
SPI_fpga_w_r_sigle/simulation/modelsim/modelsim.ini
SPI_fpga_w_r_sigle/simulation/modelsim/msim_transcript
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/_deps
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/vopt0itzh7
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/vopt1j511f
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/vopt42gvh7
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/vopt43vy0f
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/vopt7i5rh7
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/vopt8jgv0f
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/voptb36q0f
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/voptbi4m1f
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/vopte1ffi7
SPI_fpga_w_r_sigle/simulation/modelsim/rtl_work/@_opt/voptf2th1f
SPI_fpga_w_r_sig

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