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文件名称:AXI_MIG

  • 所属分类：
    source in ebook
  • 标签属性：
    [PDF]
  • 上传时间：
    2013-04-09
  • 文件大小：
    729.66kb
  • 已下载：
    1次
  • 提 供 者：
    王****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

ISE生成的AXI接口的MIG，内存控制器，语言：verilog-ISE generated the AXI interface MIG, memory controller, language: verilog
(系统自动生成,下载前可以参看下载内容)

下载文件列表

AXI_MIG/AXI_MIG.csv
AXI_MIG/datasheet.txt
AXI_MIG/docs/phy_only_support_readme.txt
AXI_MIG/docs/ug586_7Series_MIS.pdf
AXI_MIG/example_design/log.txt
AXI_MIG/example_design/par/create_ise.bat
AXI_MIG/example_design/par/ddr_ila_basic_cg.xco
AXI_MIG/example_design/par/ddr_ila_rdpath_cg.xco
AXI_MIG/example_design/par/ddr_ila_wrpath_cg.xco
AXI_MIG/example_design/par/ddr_vio_sync_async_out72_cg.xco
AXI_MIG/example_design/par/example_top.cdc
AXI_MIG/example_design/par/example_top.cpj
AXI_MIG/example_design/par/example_top.ucf
AXI_MIG/example_design/par/example_top.xdc
AXI_MIG/example_design/par/icon4_cg.xco
AXI_MIG/example_design/par/ise_flow.bat
AXI_MIG/example_design/par/makeproj.bat
AXI_MIG/example_design/par/readme.txt
AXI_MIG/example_design/par/rem_files.bat
AXI_MIG/example_design/par/rem_files.tcl
AXI_MIG/example_design/par/set_ise_prop.tcl
AXI_MIG/example_design/par/vivado.tcl
AXI_MIG/example_design/par/vivado_gui.tcl
AXI_MIG/example_design/par/xst_options.txt
AXI_MIG/example_design/rtl/example_top.v
AXI_MIG/example_design/rtl/traffic_gen/axi4_tg.v
AXI_MIG/example_design/rtl/traffic_gen/axi4_wrapper.v
AXI_MIG/example_design/rtl/traffic_gen/cmd_prbs_gen_axi.v
AXI_MIG/example_design/rtl/traffic_gen/data_gen_chk.v
AXI_MIG/example_design/rtl/traffic_gen/tg.v
AXI_MIG/example_design/sim/ddr3_model.v
AXI_MIG/example_design/sim/ddr3_model_parameters.vh
AXI_MIG/example_design/sim/isim_files.prj
AXI_MIG/example_design/sim/isim_options.tcl
AXI_MIG/example_design/sim/isim_run.bat
AXI_MIG/example_design/sim/readme.txt
AXI_MIG/example_design/sim/sim.do
AXI_MIG/example_design/sim/sim_tb_top.v
AXI_MIG/example_design/sim/wiredly.v
AXI_MIG/example_design/sim/xsim_files.prj
AXI_MIG/example_design/sim/xsim_options.tcl
AXI_MIG/example_design/sim/xsim_run.bat
AXI_MIG/example_design/synth/example_top.lso
AXI_MIG/example_design/synth/example_top.prj
AXI_MIG/mig.prj
AXI_MIG/user_design/constraints/AXI_MIG.ucf
AXI_MIG/user_design/constraints/AXI_MIG.xdc
AXI_MIG/user_design/log.txt
AXI_MIG/user_design/rtl/axi/axi_ctrl_addr_decode.v
AXI_MIG/user_design/rtl/axi/axi_ctrl_read.v
AXI_MIG/user_design/rtl/axi/axi_ctrl_reg.v
AXI_MIG/user_design/rtl/axi/axi_ctrl_reg_bank.v
AXI_MIG/user_design/rtl/axi/axi_ctrl_top.v
AXI_MIG/user_design/rtl/axi/axi_ctrl_write.v
AXI_MIG/user_design/rtl/axi/axi_mc.v
AXI_MIG/user_design/rtl/axi/axi_mc_ar_channel.v
AXI_MIG/user_design/rtl/axi/axi_mc_aw_channel.v
AXI_MIG/user_design/rtl/axi/axi_mc_b_channel.v
AXI_MIG/user_design/rtl/axi/axi_mc_cmd_arbiter.v
AXI_MIG/user_design/rtl/axi/axi_mc_cmd_fsm.v
AXI_MIG/user_design/rtl/axi/axi_mc_cmd_translator.v
AXI_MIG/user_design/rtl/axi/axi_mc_incr_cmd.v
AXI_MIG/user_design/rtl/axi/axi_mc_r_channel.v
AXI_MIG/user_design/rtl/axi/axi_mc_simple_fifo.v
AXI_MIG/user_design/rtl/axi/axi_mc_wrap_cmd.v
AXI_MIG/user_design/rtl/axi/axi_mc_wr_cmd_fsm.v
AXI_MIG/user_design/rtl/axi/axi_mc_w_channel.v
AXI_MIG/user_design/rtl/axi/ddr_axic_register_slice.v
AXI_MIG/user_design/rtl/axi/ddr_axi_register_slice.v
AXI_MIG/user_design/rtl/axi/ddr_axi_upsizer.v
AXI_MIG/user_design/rtl/axi/ddr_a_upsizer.v
AXI_MIG/user_design/rtl/axi/ddr_carry_and.v
AXI_MIG/user_design/rtl/axi/ddr_carry_latch_and.v
AXI_MIG/user_design/rtl/axi/ddr_carry_latch_or.v
AXI_MIG/user_design/rtl/axi/ddr_carry_or.v
AXI_MIG/user_design/rtl/axi/ddr_command_fifo.v
AXI_MIG/user_design/rtl/axi/ddr_comparator.v
AXI_MIG/user_design/rtl/axi/ddr_comparator_sel.v
AXI_MIG/user_design/rtl/axi/ddr_comparator_sel_static.v
AXI_MIG/user_design/rtl/axi/ddr_r_upsizer.v
AXI_MIG/user_design/rtl/axi/ddr_w_upsizer.v
AXI_MIG/user_design/rtl/AXI_MIG.v
AXI_MIG/user_design/rtl/clocking/clk_ibuf.v
AXI_MIG/user_design/rtl/clocking/infrastructure.v
AXI_MIG/user_design/rtl/clocking/iodelay_ctrl.v
AXI_MIG/user_design/rtl/controller/arb_mux.v
AXI_MIG/user_design/rtl/controller/arb_row_col.v
AXI_MIG/user_design/rtl/controller/arb_select.v
AXI_MIG/user_design/rtl/controller/bank_cntrl.v
AXI_MIG/user_design/rtl/controller/bank_common.v
AXI_MIG/user_design/rtl/controller/bank_compare.v
AXI_MIG/user_design/rtl/controller/bank_mach.v
AXI_MIG/user_design/rtl/controller/bank_queue.v
AXI_MIG/user_design/rtl/controller/bank_state.v
AXI_MIG/user_design/rtl/controller/col_mach.v
AXI_MIG/user_design/rtl/controller/mc.v
AXI_MIG/user_design/rtl/controller/rank_cntrl.v
AXI_MIG/user_design/rtl/controller/rank_common.v
AXI_MIG/user_design/rtl/controller/rank_mach.v
AXI_MIG/user_design/rtl/controller/round_robin_arb.v
AXI_MIG/user_design/rtl/ecc/ecc_buf.v
AXI_MIG/user_design/rtl/ecc/ecc_dec_fix.v
AXI_MIG/user_design/rtl/ecc/ecc_gen.v
AXI_MIG/user_design/rtl/ecc/ecc_merge_enc.v
AXI_MIG/user_design/rtl/ip_top/memc_ui_top_axi.v
AXI_MIG/user_design/rtl/ip_top/mem_intfc.v
AXI_MIG/user_design/rtl/phy/ddr_byte_group_io.v
AXI_MIG/user_design/rtl/phy/ddr_byte_lane.v
AXI_MIG/user_design/rtl/phy/ddr_calib_top.v
AXI_MIG/user_design/rtl/phy/ddr_if_post_fifo.v
AXI_MIG/user_design/rtl/phy/ddr_mc_phy.v
AXI_MIG/user_design/rtl/phy/ddr_mc_phy_wrapper.v
AXI_MIG/user_design/rtl/phy/ddr_of_pre_fifo.v
AXI_MIG/user_design/rtl/phy/ddr_phy_4lanes.v
AXI_MIG/user_design/rtl/phy/ddr_phy_ck_addr_cmd_delay.v
AXI_MIG/user_d

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