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文件名称:asic_final

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  • 上传时间:
    2013-04-11
  • 文件大小:
    266.44kb
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    1次
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Verilog 程序 实现一个简单的语音信号增强DSP设计

分为左右声道-To realize a sound de-nosing dsp using verilog
(系统自动生成,下载前可以参看下载内容)

下载文件列表

asic_final/data.in
asic_final/data.out
asic_final/data_expected.out
asic_final/FSM.v
asic_final/piso.v
asic_final/sipo.v
asic_final/testbench.vhd
asic_final/top.v
asic_final/vsim.wlf
asic_final/work/@_opt/vopt01979a
asic_final/work/@_opt/vopt04ga2j
asic_final/work/@_opt/vopt37q4qc
asic_final/work/@_opt/vopt39j17r
asic_final/work/@_opt/vopt3v6z6h
asic_final/work/@_opt/vopt4i07rk
asic_final/work/@_opt/vopt612yet
asic_final/work/@_opt/vopt6e8w5d
asic_final/work/@_opt/vopt7vn1b9
asic_final/work/@_opt/vopt7w13tg
asic_final/work/@_opt/voptah0veq
asic_final/work/@_opt/voptayxr5d
asic_final/work/@_opt/voptdejm5d
asic_final/work/@_opt/vopte1nreq
asic_final/work/@_opt/voptemetct
asic_final/work/@_opt/vopth4bkxc
asic_final/work/@_opt/vopthd6i0e
asic_final/work/@_opt/voptinfqhn
asic_final/work/@_opt/voptkzjfav
asic_final/work/@_opt/voptm40k7r
asic_final/work/@_opt/voptmk0hxc
asic_final/work/@_opt/voptr4nexc
asic_final/work/@_opt/voptrf9bav
asic_final/work/@_opt/voptrfj9gq
asic_final/work/@_opt/voptskmg7r
asic_final/work/@_opt/voptvjq5ki
asic_final/work/@_opt/voptw47bde
asic_final/work/@_opt/voptw4bd7r
asic_final/work/@_opt/voptwzy8av
asic_final/work/@_opt/voptz3h5ew
asic_final/work/@_opt/voptzf72gk
asic_final/work/@_opt/_deps
asic_final/work/@_opt1/vopt0aft8h
asic_final/work/@_opt1/vopt1597jq
asic_final/work/@_opt1/vopt271chg
asic_final/work/@_opt1/vopt2n5aie
asic_final/work/@_opt1/vopt3t4q8h
asic_final/work/@_opt1/vopt51b4fj
asic_final/work/@_opt1/vopt5gc1gi
asic_final/work/@_opt1/vopt5qc6q8
asic_final/work/@_opt1/vopt6909bd
asic_final/work/@_opt1/vopt7atj8h
asic_final/work/@_opt1/vopt7nzha4
asic_final/work/@_opt1/vopt83yyey
asic_final/work/@_opt1/vopt9446i8
asic_final/work/@_opt1/vopt95f3d4
asic_final/work/@_opt1/vopt9h01fj
asic_final/work/@_opt1/vopta6mea4
asic_final/work/@_opt1/voptc1nxej
asic_final/work/@_opt1/voptcbtv6w
asic_final/work/@_opt1/voptcfy0f6
asic_final/work/@_opt1/voptd8n3n9
asic_final/work/@_opt1/voptenaaa4
asic_final/work/@_opt1/voptf7wq2r
asic_final/work/@_opt1/voptgf1xy1
asic_final/work/@_opt1/voptgrrt1f
asic_final/work/@_opt1/voptgvqzk5
asic_final/work/@_opt1/vopth607a4
asic_final/work/@_opt1/voptjf9qkg
asic_final/work/@_opt1/voptjqhk2r
asic_final/work/@_opt1/voptkznsy1
asic_final/work/@_opt1/voptmx24xz
asic_final/work/@_opt1/voptq77h2r
asic_final/work/@_opt1/voptqfcny1
asic_final/work/@_opt1/voptqgajsc
asic_final/work/@_opt1/vopts821kw
asic_final/work/@_opt1/vopttbse6s
asic_final/work/@_opt1/voptvmtgie
asic_final/work/@_opt1/voptvqzjn2
asic_final/work/@_opt1/voptw36xtq
asic_final/work/@_opt1/vopty5gdie
asic_final/work/@_opt1/vopty7va2m
asic_final/work/@_opt1/voptyeig9e
asic_final/work/@_opt1/_deps
asic_final/work/fsm/verilog.prw
asic_final/work/fsm/verilog.psm
asic_final/work/fsm/_primary.dat
asic_final/work/fsm/_primary.dbs
asic_final/work/fsm/_primary.vhd
asic_final/work/msdap/verilog.prw
asic_final/work/msdap/verilog.psm
asic_final/work/msdap/_primary.dat
asic_final/work/msdap/_primary.dbs
asic_final/work/msdap/_primary.vhd
asic_final/work/piso/verilog.prw
asic_final/work/piso/verilog.psm
asic_final/work/piso/_primary.dat
asic_final/work/piso/_primary.dbs
asic_final/work/piso/_primary.vhd
asic_final/work/sipo/verilog.prw
asic_final/work/sipo/verilog.psm
asic_final/work/sipo/_primary.dat
asic_final/work/sipo/_primary.dbs
asic_final/work/sipo/_primary.vhd
asic_final/work/testbench/examine.dat
asic_final/work/testbench/examine.dbs
asic_final/work/testbench/examine.prw
asic_final/work/testbench/examine.psm
asic_final/work/testbench/_primary.dat
asic_final/work/testbench/_primary.dbs
asic_final/work/working/verilog.prw
asic_final/work/working/verilog.psm
asic_final/work/working/_primary.dat
asic_final/work/working/_primary.dbs
asic_final/work/working/_primary.vhd
asic_final/work/_info
asic_final/work/_vmake
asic_final/working.v
asic_final/work/@_opt
asic_final/work/@_opt1
asic_final/work/fsm
asic_final/work/msdap
asic_final/work/piso
asic_final/work/sipo
asic_final/work/testbench
asic_final/work/working
asic_final/work/_temp
asic_final/work
asic_final

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