文件名称:rs232_verilog
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- 上传时间:2013-04-12
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文件大小:424.58kb
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FPGA实现串口通信实验,用verilog实现串口的发送和接收数据-FPGA Implementation of serial communication experiment, the serial port to send and receive data with verilog
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下载文件列表
uart_verilog/
uart_verilog/db/
uart_verilog/db/logic_util_heursitic.dat
uart_verilog/db/my_uart_top.(0).cnf.cdb
uart_verilog/db/my_uart_top.(0).cnf.hdb
uart_verilog/db/my_uart_top.(1).cnf.cdb
uart_verilog/db/my_uart_top.(1).cnf.hdb
uart_verilog/db/my_uart_top.(2).cnf.cdb
uart_verilog/db/my_uart_top.(2).cnf.hdb
uart_verilog/db/my_uart_top.(3).cnf.cdb
uart_verilog/db/my_uart_top.(3).cnf.hdb
uart_verilog/db/my_uart_top.asm.qmsg
uart_verilog/db/my_uart_top.asm_labs.ddb
uart_verilog/db/my_uart_top.cbx.xml
uart_verilog/db/my_uart_top.cmp.cdb
uart_verilog/db/my_uart_top.cmp.hdb
uart_verilog/db/my_uart_top.cmp.kpt
uart_verilog/db/my_uart_top.cmp.logdb
uart_verilog/db/my_uart_top.cmp.rdb
uart_verilog/db/my_uart_top.cmp.tdb
uart_verilog/db/my_uart_top.cmp0.ddb
uart_verilog/db/my_uart_top.cmp2.ddb
uart_verilog/db/my_uart_top.db_info
uart_verilog/db/my_uart_top.eco.cdb
uart_verilog/db/my_uart_top.fit.qmsg
uart_verilog/db/my_uart_top.hier_info
uart_verilog/db/my_uart_top.hif
uart_verilog/db/my_uart_top.lpc.html
uart_verilog/db/my_uart_top.lpc.rdb
uart_verilog/db/my_uart_top.lpc.txt
uart_verilog/db/my_uart_top.map.cdb
uart_verilog/db/my_uart_top.map.hdb
uart_verilog/db/my_uart_top.map.logdb
uart_verilog/db/my_uart_top.map.qmsg
uart_verilog/db/my_uart_top.pre_map.cdb
uart_verilog/db/my_uart_top.pre_map.hdb
uart_verilog/db/my_uart_top.rtlv.hdb
uart_verilog/db/my_uart_top.rtlv_sg.cdb
uart_verilog/db/my_uart_top.rtlv_sg_swap.cdb
uart_verilog/db/my_uart_top.sgdiff.cdb
uart_verilog/db/my_uart_top.sgdiff.hdb
uart_verilog/db/my_uart_top.sld_design_entry.sci
uart_verilog/db/my_uart_top.sld_design_entry_dsc.sci
uart_verilog/db/my_uart_top.syn_hier_info
uart_verilog/db/my_uart_top.tan.qmsg
uart_verilog/db/my_uart_top.tis_db_list.ddb
uart_verilog/db/my_uart_top.tmw_info
uart_verilog/db/my_uart_top_global_asgn_op.abo
uart_verilog/db/prev_cmp_my_uart_top.asm.qmsg
uart_verilog/db/prev_cmp_my_uart_top.fit.qmsg
uart_verilog/db/prev_cmp_my_uart_top.map.qmsg
uart_verilog/db/prev_cmp_my_uart_top.qmsg
uart_verilog/db/prev_cmp_my_uart_top.tan.qmsg
uart_verilog/incremental_db/
uart_verilog/incremental_db/compiled_partitions/
uart_verilog/incremental_db/compiled_partitions/my_uart_top.root_partition.map.kpt
uart_verilog/incremental_db/README
uart_verilog/my_uart_rx.v
uart_verilog/my_uart_rx.v.bak
uart_verilog/my_uart_top.asm.rpt
uart_verilog/my_uart_top.cdf
uart_verilog/my_uart_top.done
uart_verilog/my_uart_top.dpf
uart_verilog/my_uart_top.fit.rpt
uart_verilog/my_uart_top.fit.smsg
uart_verilog/my_uart_top.fit.summary
uart_verilog/my_uart_top.flow.rpt
uart_verilog/my_uart_top.jpg
uart_verilog/my_uart_top.map.rpt
uart_verilog/my_uart_top.map.smsg
uart_verilog/my_uart_top.map.summary
uart_verilog/my_uart_top.pin
uart_verilog/my_uart_top.pof
uart_verilog/my_uart_top.qpf
uart_verilog/my_uart_top.qsf
uart_verilog/my_uart_top.qws
uart_verilog/my_uart_top.sof
uart_verilog/my_uart_top.tan.rpt
uart_verilog/my_uart_top.tan.summary
uart_verilog/my_uart_top.v
uart_verilog/my_uart_top_assignment_defaults.qdf
uart_verilog/my_uart_tx.v
uart_verilog/my_uart_tx.v.bak
uart_verilog/osh.tcl
uart_verilog/speed_select.v
uart_verilog/db/
uart_verilog/db/logic_util_heursitic.dat
uart_verilog/db/my_uart_top.(0).cnf.cdb
uart_verilog/db/my_uart_top.(0).cnf.hdb
uart_verilog/db/my_uart_top.(1).cnf.cdb
uart_verilog/db/my_uart_top.(1).cnf.hdb
uart_verilog/db/my_uart_top.(2).cnf.cdb
uart_verilog/db/my_uart_top.(2).cnf.hdb
uart_verilog/db/my_uart_top.(3).cnf.cdb
uart_verilog/db/my_uart_top.(3).cnf.hdb
uart_verilog/db/my_uart_top.asm.qmsg
uart_verilog/db/my_uart_top.asm_labs.ddb
uart_verilog/db/my_uart_top.cbx.xml
uart_verilog/db/my_uart_top.cmp.cdb
uart_verilog/db/my_uart_top.cmp.hdb
uart_verilog/db/my_uart_top.cmp.kpt
uart_verilog/db/my_uart_top.cmp.logdb
uart_verilog/db/my_uart_top.cmp.rdb
uart_verilog/db/my_uart_top.cmp.tdb
uart_verilog/db/my_uart_top.cmp0.ddb
uart_verilog/db/my_uart_top.cmp2.ddb
uart_verilog/db/my_uart_top.db_info
uart_verilog/db/my_uart_top.eco.cdb
uart_verilog/db/my_uart_top.fit.qmsg
uart_verilog/db/my_uart_top.hier_info
uart_verilog/db/my_uart_top.hif
uart_verilog/db/my_uart_top.lpc.html
uart_verilog/db/my_uart_top.lpc.rdb
uart_verilog/db/my_uart_top.lpc.txt
uart_verilog/db/my_uart_top.map.cdb
uart_verilog/db/my_uart_top.map.hdb
uart_verilog/db/my_uart_top.map.logdb
uart_verilog/db/my_uart_top.map.qmsg
uart_verilog/db/my_uart_top.pre_map.cdb
uart_verilog/db/my_uart_top.pre_map.hdb
uart_verilog/db/my_uart_top.rtlv.hdb
uart_verilog/db/my_uart_top.rtlv_sg.cdb
uart_verilog/db/my_uart_top.rtlv_sg_swap.cdb
uart_verilog/db/my_uart_top.sgdiff.cdb
uart_verilog/db/my_uart_top.sgdiff.hdb
uart_verilog/db/my_uart_top.sld_design_entry.sci
uart_verilog/db/my_uart_top.sld_design_entry_dsc.sci
uart_verilog/db/my_uart_top.syn_hier_info
uart_verilog/db/my_uart_top.tan.qmsg
uart_verilog/db/my_uart_top.tis_db_list.ddb
uart_verilog/db/my_uart_top.tmw_info
uart_verilog/db/my_uart_top_global_asgn_op.abo
uart_verilog/db/prev_cmp_my_uart_top.asm.qmsg
uart_verilog/db/prev_cmp_my_uart_top.fit.qmsg
uart_verilog/db/prev_cmp_my_uart_top.map.qmsg
uart_verilog/db/prev_cmp_my_uart_top.qmsg
uart_verilog/db/prev_cmp_my_uart_top.tan.qmsg
uart_verilog/incremental_db/
uart_verilog/incremental_db/compiled_partitions/
uart_verilog/incremental_db/compiled_partitions/my_uart_top.root_partition.map.kpt
uart_verilog/incremental_db/README
uart_verilog/my_uart_rx.v
uart_verilog/my_uart_rx.v.bak
uart_verilog/my_uart_top.asm.rpt
uart_verilog/my_uart_top.cdf
uart_verilog/my_uart_top.done
uart_verilog/my_uart_top.dpf
uart_verilog/my_uart_top.fit.rpt
uart_verilog/my_uart_top.fit.smsg
uart_verilog/my_uart_top.fit.summary
uart_verilog/my_uart_top.flow.rpt
uart_verilog/my_uart_top.jpg
uart_verilog/my_uart_top.map.rpt
uart_verilog/my_uart_top.map.smsg
uart_verilog/my_uart_top.map.summary
uart_verilog/my_uart_top.pin
uart_verilog/my_uart_top.pof
uart_verilog/my_uart_top.qpf
uart_verilog/my_uart_top.qsf
uart_verilog/my_uart_top.qws
uart_verilog/my_uart_top.sof
uart_verilog/my_uart_top.tan.rpt
uart_verilog/my_uart_top.tan.summary
uart_verilog/my_uart_top.v
uart_verilog/my_uart_top_assignment_defaults.qdf
uart_verilog/my_uart_tx.v
uart_verilog/my_uart_tx.v.bak
uart_verilog/osh.tcl
uart_verilog/speed_select.v
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