文件名称:final
-
所属分类:
- 标签属性:
- 上传时间:2013-04-13
-
文件大小:725byte
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
频率计设计的各个模块连接的总程序,即把分频器、控制器、计数器、闸门控制、锁存器、显示器都连接起来,测试频率范围为:10Hz~100MHz 第一档:闸门时间为1S时,最大读数为999.999KHz
第二档:闸门时间为0.1S时,最大读数为9999.99KHz
第三档:闸门时间为0.01S时,最大读数为99999.9KHz。
用六位BCD七段数码管显示读数。-The various modules connected to the total program, frequency meter design that are connected to the divider, controllers, counters, gate control, latches, display, test frequency range of: 10Hz ~~ 100MHz speed: gate time 1S when maximum readings 999.999KHz second gear: the gate time 0.1S maximum reading 9999.99KHz third tranche: gate time 0.01S, the maximum readings for 99999.9KHz. Readings with six BCD seven segment LED display.
第二档:闸门时间为0.1S时,最大读数为9999.99KHz
第三档:闸门时间为0.01S时,最大读数为99999.9KHz。
用六位BCD七段数码管显示读数。-The various modules connected to the total program, frequency meter design that are connected to the divider, controllers, counters, gate control, latches, display, test frequency range of: 10Hz ~~ 100MHz speed: gate time 1S when maximum readings 999.999KHz second gear: the gate time 0.1S maximum reading 9999.99KHz third tranche: gate time 0.01S, the maximum readings for 99999.9KHz. Readings with six BCD seven segment LED display.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
final.vhd
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.