文件名称:mea_word
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- 上传时间:2013-04-15
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文件大小:121.48kb
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自己编的处理器verilog源码,实现了8位处理器的功能,包含流水线-mcu verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
mea_word/addr_gen.doc
mea_word/bilinear.doc
mea_word/boundary_chk.doc
mea_word/chk_pe.doc
mea_word/clk_gate_ran.doc
mea_word/intra_sad.doc
mea_word/linear_x.doc
mea_word/linear_y.doc
mea_word/master_a.doc
mea_word/master_b.doc
mea_word/mea_ctl.doc
mea_word/mea_slave.doc
mea_word/mea_top.doc
mea_word/mea——tb.doc
mea_word/mem_ctl.doc
mea_word/mv_decoder.doc
mea_word/pe_array.doc
mea_word/process_element.doc
mea_word
mea_word/bilinear.doc
mea_word/boundary_chk.doc
mea_word/chk_pe.doc
mea_word/clk_gate_ran.doc
mea_word/intra_sad.doc
mea_word/linear_x.doc
mea_word/linear_y.doc
mea_word/master_a.doc
mea_word/master_b.doc
mea_word/mea_ctl.doc
mea_word/mea_slave.doc
mea_word/mea_top.doc
mea_word/mea——tb.doc
mea_word/mem_ctl.doc
mea_word/mv_decoder.doc
mea_word/pe_array.doc
mea_word/process_element.doc
mea_word
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