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文件名称:Timer

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-04-15
  • 文件大小：
    1.61mb
  • 已下载：
    0次
  • 提 供 者：
    s*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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Verilog编写的多功能秒表，Quartus仿真及硬件测试通过。-Verilog prepared by the multi-function stopwatch, Quartus simulation and hardware testing through.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

div2000.v
div2000.v.bak
monitor_7.bsf
monitor7.v
monitor7.v.bak
Sweep.bsf
sweep.v
sweep.v.bak
Verilog6.v
Verilog8.v
Verilog8.v.bak
Waveform3.vwf
db/AdvDesign.db_info
db/AdvDesign.tis_db_list.ddb
db/AdvDesign.(0).cnf.cdb
db/AdvDesign.(0).cnf.hdb
db/AdvDesign.(2).cnf.cdb
db/AdvDesign.cbx.xml
db/AdvDesign.hif
db/AdvDesign.(2).cnf.hdb
db/AdvDesign.(3).cnf.cdb
db/AdvDesign.hier_info
db/AdvDesign.(3).cnf.hdb
db/AdvDesign.(5).cnf.cdb
db/AdvDesign.(5).cnf.hdb
db/AdvDesign.(6).cnf.cdb
db/AdvDesign.(6).cnf.hdb
db/AdvDesign.(7).cnf.cdb
db/AdvDesign.psp
db/AdvDesign.dbp
db/AdvDesign.pss
db/AdvDesign.(7).cnf.hdb
db/AdvDesign.(8).cnf.cdb
db/AdvDesign.(8).cnf.hdb
db/AdvDesign.(9).cnf.cdb
db/AdvDesign.syn_hier_info
db/AdvDesign.(9).cnf.hdb
db/AdvDesign.(10).cnf.cdb
db/AdvDesign.(10).cnf.hdb
db/AdvDesign.rtlv_sg.cdb
db/AdvDesign.rtlv.hdb
db/AdvDesign.map.ecobp
db/AdvDesign.pre_map.hdb
db/AdvDesign.rtlv_sg_swap.cdb
db/AdvDesign.pre_map.cdb
db/AdvDesign.smp_dump.txt
db/AdvDesign.map_bb.logdb
db/AdvDesign.sgdiff.cdb
db/AdvDesign.sgdiff.hdb
db/prev_cmp_AdvDesign.sim.qmsg
db/AdvDesign.fit.qmsg
db/AdvDesign.cmp.logdb
db/AdvDesign.map_bb.cdb
db/AdvDesign.map_bb.hdb
db/AdvDesign.map.logdb
db/AdvDesign.map.cdb
db/AdvDesign.map.hdb
db/AdvDesign.map.bpm
db/AdvDesign.cmp.bpm
db/AdvDesign.asm.qmsg
db/AdvDesign.sta.qmsg
db/AdvDesign.cmp.cdb
db/AdvDesign.tiscmp.slow_1200mv_85c.ddb
db/prev_cmp_AdvDesign.qmsg
db/AdvDesign.signalprobe.cdb
db/AdvDesign.asm_labs.ddb
db/AdvDesign.cmp.ecobp
db/AdvDesign.cmp_bb.logdb
db/AdvDesign.cmp_bb.rcf
db/AdvDesign.cmp_bb.cdb
db/AdvDesign.cmp_bb.hdb
db/AdvDesign.sim.qmsg
db/AdvDesign.cuda_io_sim_cache.ss_85.hsd
db/AdvDesign.cmp.hdb
db/AdvDesign.sta.rdb
db/AdvDesign.(11).cnf.cdb
db/AdvDesign.(11).cnf.hdb
db/AdvDesign.tiscmp.slow_1200mv_0c.ddb
db/AdvDesign.tiscmp.fast_1200mv_0c.ddb
db/AdvDesign.eco.cdb
db/AdvDesign.cuda_io_sim_cache.ff_0.hsd
db/AdvDesign.cmp.rdb
db/AdvDesign.fnsim.qmsg
db/AdvDesign.fnsim.cdb
db/AdvDesign.fnsim.hdb
db/AdvDesign.sld_design_entry_dsc.sci
db/AdvDesign.sim.hdb
db/AdvDesign.sld_design_entry.sci
db/AdvDesign.simfam
db/AdvDesign.eds_overflow
db/wed.wsf
db/AdvDesign.(16).cnf.cdb
db/AdvDesign.(16).cnf.hdb
db/AdvDesign.(1).cnf.cdb
db/AdvDesign.(1).cnf.hdb
db/AdvDesign.(4).cnf.cdb
db/AdvDesign.(4).cnf.hdb
db/AdvDesign.sim.cvwf
db/prev_cmp_AdvDesign.map.qmsg
db/prev_cmp_AdvDesign.fit.qmsg
db/prev_cmp_AdvDesign.asm.qmsg
db/prev_cmp_AdvDesign.sta.qmsg
db/AdvDesign.map.qmsg
AdvDesign.asm.rpt
AdvDesign.bdf
AdvDesign.bsf
AdvDesign.done
AdvDesign.dpf
AdvDesign.fit.rpt
AdvDesign.fit.smsg
AdvDesign.fit.summary
AdvDesign.flow.rpt
AdvDesign.map.rpt
AdvDesign.map.smsg
AdvDesign.map.summary
AdvDesign.pin
AdvDesign.pof
AdvDesign.qpf
AdvDesign.qsf
AdvDesign.qws
AdvDesign.sim.cvwf
AdvDesign.sim.rpt
AdvDesign.sof
AdvDesign.sta.rpt
AdvDesign.sta.summary
AdvDesign.v
AdvDesign.v.bak
AdvDesign.vwf
block1.bdf
controlclk.bsf
controlclk.v
controlclk.v.bak
countdown.bsf
countdown.v
countdown.v.bak
div100.bsf
div100.v
div100.v.bak
div2000.bsf
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