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文件名称:PLL

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-04-20
  • 文件大小：
    224.78kb
  • 已下载：
    0次
  • 提 供 者：
    李***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

quartus II中IP核的使用案例，在程序里边调用了PLL核进行时钟的管理。-Quartus II IP core use cases, called in the program inside the PLL core clock management.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

PLL/db/pll_prj.(0).cnf.cdb
PLL/db/pll_prj.(0).cnf.hdb
PLL/db/pll_prj.(1).cnf.cdb
PLL/db/pll_prj.(1).cnf.hdb
PLL/db/pll_prj.(2).cnf.cdb
PLL/db/pll_prj.(2).cnf.hdb
PLL/db/pll_prj.cbx.xml
PLL/db/pll_prj.cmp.hdb
PLL/db/pll_prj.cmp.rdb
PLL/db/pll_prj.cmp_merge.kpt
PLL/db/pll_prj.db_info
PLL/db/pll_prj.eco.cdb
PLL/db/pll_prj.eda.qmsg
PLL/db/pll_prj.hier_info
PLL/db/pll_prj.hif
PLL/db/pll_prj.lpc.html
PLL/db/pll_prj.lpc.rdb
PLL/db/pll_prj.lpc.txt
PLL/db/pll_prj.map.bpm
PLL/db/pll_prj.map.cdb
PLL/db/pll_prj.map.ecobp
PLL/db/pll_prj.map.hdb
PLL/db/pll_prj.map.kpt
PLL/db/pll_prj.map.logdb
PLL/db/pll_prj.map.qmsg
PLL/db/pll_prj.map_bb.cdb
PLL/db/pll_prj.map_bb.hdb
PLL/db/pll_prj.map_bb.logdb
PLL/db/pll_prj.pre_map.cdb
PLL/db/pll_prj.pre_map.hdb
PLL/db/pll_prj.rtlv.hdb
PLL/db/pll_prj.rtlv_sg.cdb
PLL/db/pll_prj.rtlv_sg_swap.cdb
PLL/db/pll_prj.sgdiff.cdb
PLL/db/pll_prj.sgdiff.hdb
PLL/db/pll_prj.sld_design_entry.sci
PLL/db/pll_prj.sld_design_entry_dsc.sci
PLL/db/pll_prj.syn_hier_info
PLL/db/pll_prj.tis_db_list.ddb
PLL/db/pll_prj.tmw_info
PLL/db/prev_cmp_pll_prj.map.qmsg
PLL/db/prev_cmp_pll_prj.qmsg
PLL/incremental_db/compiled_partitions/pll_prj.root_partition.map.atm
PLL/incremental_db/compiled_partitions/pll_prj.root_partition.map.dpi
PLL/incremental_db/compiled_partitions/pll_prj.root_partition.map.hdbx
PLL/incremental_db/compiled_partitions/pll_prj.root_partition.map.kpt
PLL/incremental_db/compiled_partitions/pll_prj.root_partition.merge_hb.atm
PLL/incremental_db/README
PLL/pll_ctrl.bsf
PLL/pll_ctrl.ppf
PLL/pll_ctrl.qip
PLL/pll_ctrl.v
PLL/pll_ctrl_bb.v
PLL/pll_ctrl_inst.v
PLL/pll_ctrl_wave0.jpg
PLL/pll_ctrl_waveforms.html
PLL/pll_prj.done
PLL/pll_prj.eda.rpt
PLL/pll_prj.flow.rpt
PLL/pll_prj.map.rpt
PLL/pll_prj.map.summary
PLL/pll_prj.qpf
PLL/pll_prj.qsf
PLL/pll_prj.qws
PLL/pll_prj.v
PLL/pll_prj_nativelink_simulation.rpt
PLL/simulation/modelsim/modelsim.ini
PLL/simulation/modelsim/msim_transcript
PLL/simulation/modelsim/pll_prj.vt
PLL/simulation/modelsim/pll_prj.vt.bak
PLL/simulation/modelsim/pll_prj_run_msim_rtl_verilog.do
PLL/simulation/modelsim/pll_prj_run_msim_rtl_verilog.do.bak
PLL/simulation/modelsim/rtl_work/pll_ctrl/verilog.psm
PLL/simulation/modelsim/rtl_work/pll_ctrl/_primary.dat
PLL/simulation/modelsim/rtl_work/pll_ctrl/_primary.dbs
PLL/simulation/modelsim/rtl_work/pll_ctrl/_primary.vhd
PLL/simulation/modelsim/rtl_work/pll_prj/verilog.psm
PLL/simulation/modelsim/rtl_work/pll_prj/_primary.dat
PLL/simulation/modelsim/rtl_work/pll_prj/_primary.dbs
PLL/simulation/modelsim/rtl_work/pll_prj/_primary.vhd
PLL/simulation/modelsim/rtl_work/pll_prj_vlg_tst/verilog.psm
PLL/simulation/modelsim/rtl_work/pll_prj_vlg_tst/_primary.dat
PLL/simulation/modelsim/rtl_work/pll_prj_vlg_tst/_primary.dbs
PLL/simulation/modelsim/rtl_work/pll_prj_vlg_tst/_primary.vhd
PLL/simulation/modelsim/rtl_work/_info
PLL/simulation/modelsim/rtl_work/_vmake
PLL/simulation/modelsim/vsim.wlf
PLL/simulation/modelsim/rtl_work/pll_ctrl
PLL/simulation/modelsim/rtl_work/pll_prj
PLL/simulation/modelsim/rtl_work/pll_prj_vlg_tst
PLL/simulation/modelsim/rtl_work/_temp
PLL/simulation/modelsim/rtl_work
PLL/incremental_db/compiled_partitions
PLL/simulation/modelsim
PLL/db
PLL/incremental_db
PLL/simulation
PLL

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