CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:uart_state

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-04-23
  • 文件大小：
    3.16mb
  • 已下载：
    0次
  • 提 供 者：
    xuxin*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于状态机编写的串口通信实验，编程语言是Verilog HDL，可发送八位数据，在Altera的EP4CE15F17C8芯片上验证成功。（与另一个发送256位不同的是这个代码比较突出状态机的使用）。-Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verify on Altera' s EP4CE15F17C8 chip. (Sent with another 256 different code more prominent use of state machines).
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart_lab/db/logic_util_heursitic.dat
uart_lab/db/prev_cmp_uart.qmsg
uart_lab/db/uart.(0).cnf.cdb
uart_lab/db/uart.(0).cnf.hdb
uart_lab/db/uart.(1).cnf.cdb
uart_lab/db/uart.(1).cnf.hdb
uart_lab/db/uart.(2).cnf.cdb
uart_lab/db/uart.(2).cnf.hdb
uart_lab/db/uart.(3).cnf.cdb
uart_lab/db/uart.(3).cnf.hdb
uart_lab/db/uart.ace_cmp.bpm
uart_lab/db/uart.ace_cmp.cdb
uart_lab/db/uart.ace_cmp.hdb
uart_lab/db/uart.amm.cdb
uart_lab/db/uart.asm.qmsg
uart_lab/db/uart.asm.rdb
uart_lab/db/uart.asm_labs.ddb
uart_lab/db/uart.atom.rvd
uart_lab/db/uart.cbx.xml
uart_lab/db/uart.cmp.bpm
uart_lab/db/uart.cmp.cdb
uart_lab/db/uart.cmp.hdb
uart_lab/db/uart.cmp.kpt
uart_lab/db/uart.cmp.logdb
uart_lab/db/uart.cmp.rdb
uart_lab/db/uart.cmp_merge.kpt
uart_lab/db/uart.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
uart_lab/db/uart.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
uart_lab/db/uart.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
uart_lab/db/uart.db_info
uart_lab/db/uart.eco.cdb
uart_lab/db/uart.eda.qmsg
uart_lab/db/uart.fit.qmsg
uart_lab/db/uart.hier_info
uart_lab/db/uart.hif
uart_lab/db/uart.idb.cdb
uart_lab/db/uart.lpc.html
uart_lab/db/uart.lpc.rdb
uart_lab/db/uart.lpc.txt
uart_lab/db/uart.map.bpm
uart_lab/db/uart.map.cdb
uart_lab/db/uart.map.hdb
uart_lab/db/uart.map.kpt
uart_lab/db/uart.map.logdb
uart_lab/db/uart.map.qmsg
uart_lab/db/uart.map_bb.cdb
uart_lab/db/uart.map_bb.hdb
uart_lab/db/uart.map_bb.logdb
uart_lab/db/uart.pre_map.cdb
uart_lab/db/uart.pre_map.hdb
uart_lab/db/uart.rpp.qmsg
uart_lab/db/uart.rtlv.hdb
uart_lab/db/uart.rtlv_sg.cdb
uart_lab/db/uart.rtlv_sg_swap.cdb
uart_lab/db/uart.sgate.rvd
uart_lab/db/uart.sgate_sm.rvd
uart_lab/db/uart.sgdiff.cdb
uart_lab/db/uart.sgdiff.hdb
uart_lab/db/uart.sld_design_entry.sci
uart_lab/db/uart.sld_design_entry_dsc.sci
uart_lab/db/uart.smart_action.txt
uart_lab/db/uart.smp_dump.txt
uart_lab/db/uart.sta.qmsg
uart_lab/db/uart.sta.rdb
uart_lab/db/uart.sta_cmp.8_slow_1200mv_85c.tdb
uart_lab/db/uart.syn_hier_info
uart_lab/db/uart.tiscmp.fastest_slow_1200mv_0c.ddb
uart_lab/db/uart.tiscmp.fastest_slow_1200mv_85c.ddb
uart_lab/db/uart.tiscmp.fast_1200mv_0c.ddb
uart_lab/db/uart.tiscmp.slow_1200mv_0c.ddb
uart_lab/db/uart.tiscmp.slow_1200mv_85c.ddb
uart_lab/db/uart.tis_db_list.ddb
uart_lab/db/uart.tmw_info
uart_lab/incremental_db/compiled_partitions/uart.db_info
uart_lab/incremental_db/compiled_partitions/uart.root_partition.cmp.cdb
uart_lab/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp
uart_lab/incremental_db/compiled_partitions/uart.root_partition.cmp.hdb
uart_lab/incremental_db/compiled_partitions/uart.root_partition.cmp.kpt
uart_lab/incremental_db/compiled_partitions/uart.root_partition.cmp.logdb
uart_lab/incremental_db/compiled_partitions/uart.root_partition.cmp.rcfdb
uart_lab/incremental_db/compiled_partitions/uart.root_partition.map.cdb
uart_lab/incremental_db/compiled_partitions/uart.root_partition.map.dpi
uart_lab/incremental_db/compiled_partitions/uart.root_partition.map.hbdb.cdb
uart_lab/incremental_db/compiled_partitions/uart.root_partition.map.hbdb.hb_info
uart_lab/incremental_db/compiled_partitions/uart.root_partition.map.hbdb.hdb
uart_lab/incremental_db/compiled_partitions/uart.root_partition.map.hbdb.sig
uart_lab/incremental_db/compiled_partitions/uart.root_partition.map.hdb
uart_lab/incremental_db/compiled_partitions/uart.root_partition.map.kpt
uart_lab/incremental_db/README
uart_lab/simulation/modelsim/uart.sft
uart_lab/simulation/modelsim/uart.vo
uart_lab/simulation/modelsim/uart_8_1200mv_0c_slow.vo
uart_lab/simulation/modelsim/uart_8_1200mv_0c_v_slow.sdo
uart_lab/simulation/modelsim/uart_8_1200mv_85c_slow.vo
uart_lab/simulation/modelsim/uart_8_1200mv_85c_v_slow.sdo
uart_lab/simulation/modelsim/uart_min_1200mv_0c_fast.vo
uart_lab/simulation/modelsim/uart_min_1200mv_0c_v_fast.sdo
uart_lab/simulation/modelsim/uart_modelsim.xrf
uart_lab/simulation/modelsim/uart_v.sdo
uart_lab/uart.asm.rpt
uart_lab/uart.done
uart_lab/uart.eda.rpt
uart_lab/uart.fit.rpt
uart_lab/uart.fit.smsg
uart_lab/uart.fit.summary
uart_lab/uart.flow.rpt
uart_lab/uart.map.rpt
uart_lab/uart.map.summary
uart_lab/uart.pin
uart_lab/uart.qpf
uart_lab/uart.qsf
uart_lab/uart.sof
uart_lab/uart.sta.rpt
uart_lab/uart.sta.summary
uart_lab/uart_baud.v
uart_lab/uart_baud.v.bak
uart_lab/uart_rx.v
uart_lab/uart_rx.v.bak
uart_lab/uart_top.v
uart_lab/uart_top.v.bak
uart_lab/uart_tx.v
uart_lab/uart_tx.v.bak
uart_lab/incremental_db/compiled_partitions
uart_lab/simulation/modelsim
uart_lab/db
uart_lab/incremental_db
uart_lab/simulation
uart_lab

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com