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文件名称:UART

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  • 上传时间:
    2013-04-25
  • 文件大小:
    1.09mb
  • 已下载:
    0次
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  • 下载说明:
    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

UART --串口发送与接收verilog代码,适用于QUATUS II 开发环境下,适合verilog入门的学员-UART- on serial port ,send and receive signal, suitable for QUATUS II development environment for Verilog entry students
(系统自动生成,下载前可以参看下载内容)

下载文件列表

UART/Doc/sscom.ini
UART/Doc/sscom32.exe
UART/Doc/UART控制器设计说明.doc
UART/Doc/xapp341.pdf
UART/func_sim/rcvr.v
UART/func_sim/transcript
UART/func_sim/txmit.v
UART/func_sim/txmit_tf.do
UART/func_sim/uart.cr.mti
UART/func_sim/uart.mpf
UART/func_sim/uart.v
UART/func_sim/uart_if.v
UART/func_sim/uart_tb.do
UART/func_sim/uart_tb.v
UART/func_sim/uart_tb_fixed.do
UART/func_sim/vish_stacktrace.vstf
UART/func_sim/vsim.wlf
UART/func_sim/wave.do
UART/func_sim/work/@u@a@r@t_tb/verilog.asm
UART/func_sim/work/@u@a@r@t_tb/_primary.dat
UART/func_sim/work/@u@a@r@t_tb/_primary.vhd
UART/func_sim/work/rcvr/verilog.asm
UART/func_sim/work/rcvr/_primary.dat
UART/func_sim/work/rcvr/_primary.vhd
UART/func_sim/work/txmit/verilog.asm
UART/func_sim/work/txmit/_primary.dat
UART/func_sim/work/txmit/_primary.vhd
UART/func_sim/work/uart/verilog.asm
UART/func_sim/work/uart/_primary.dat
UART/func_sim/work/uart/_primary.vhd
UART/func_sim/work/uart_if/verilog.asm
UART/func_sim/work/uart_if/_primary.dat
UART/func_sim/work/uart_if/_primary.vhd
UART/func_sim/work/_info
UART/physical/altclklock0.bsf
UART/physical/altclklock0.v
UART/physical/altclklock0_bb.v
UART/physical/async_transmitter.bsf
UART/physical/cmp_state.ini
UART/physical/db/altsyncram_2dq.tdf
UART/physical/db/altsyncram_8tj.tdf
UART/physical/db/altsyncram_9un.tdf
UART/physical/db/altsyncram_eh31.tdf
UART/physical/db/altsyncram_g5q.tdf
UART/physical/db/cntr_cs6.tdf
UART/physical/db/cntr_gs6.tdf
UART/physical/db/cntr_ub7.tdf
UART/physical/db/cntr_vt6.tdf
UART/physical/db/uart_if(0).cnf.cdb
UART/physical/db/uart_if(0).cnf.hdb
UART/physical/db/uart_if(1).cnf.cdb
UART/physical/db/uart_if(1).cnf.hdb
UART/physical/db/uart_if(2).cnf.cdb
UART/physical/db/uart_if(2).cnf.hdb
UART/physical/db/uart_if(3).cnf.cdb
UART/physical/db/uart_if(3).cnf.hdb
UART/physical/db/uart_if(4).cnf.cdb
UART/physical/db/uart_if(4).cnf.hdb
UART/physical/db/uart_if(5).cnf.cdb
UART/physical/db/uart_if(5).cnf.hdb
UART/physical/db/uart_if(6).cnf.cdb
UART/physical/db/uart_if(6).cnf.hdb
UART/physical/db/uart_if(7).cnf.cdb
UART/physical/db/uart_if(7).cnf.hdb
UART/physical/db/uart_if(8).cnf.cdb
UART/physical/db/uart_if(8).cnf.hdb
UART/physical/db/uart_if(9).cnf.cdb
UART/physical/db/uart_if(9).cnf.hdb
UART/physical/db/uart_if.db_info
UART/physical/db/uart_if.sld_design_entry.sci
UART/physical/db/uart_if_cmp.qrpt
UART/physical/db/uart_if_hier_info
UART/physical/db/uart_if_syn_hier_info
UART/physical/div.bsf
UART/physical/div_2.bsf
UART/physical/div_2.v
UART/physical/filter.bsf
UART/physical/LED_flush.bsf
UART/physical/rcvr.bsf
UART/physical/simulation/modelsim/cyclone_atoms.v
UART/physical/simulation/modelsim/uart_if.vo
UART/physical/simulation/modelsim/uart_if_modelsim.xrf
UART/physical/simulation/modelsim/uart_if_v.sdo
UART/physical/simulation/modelsim/uart_post.cr.mti
UART/physical/simulation/modelsim/uart_post.mpf
UART/physical/simulation/modelsim/vsim.wlf
UART/physical/simulation/modelsim/work/@p@r@i@m_@d@f@f@e/verilog.asm
UART/physical/simulation/modelsim/work/@p@r@i@m_@d@f@f@e/_primary.dat
UART/physical/simulation/modelsim/work/@p@r@i@m_@d@f@f@e/_primary.vhd
UART/physical/simulation/modelsim/work/@u@a@r@t_tb/verilog.asm
UART/physical/simulation/modelsim/work/@u@a@r@t_tb/_primary.dat
UART/physical/simulation/modelsim/work/@u@a@r@t_tb/_primary.vhd
UART/physical/simulation/modelsim/work/and1/verilog.asm
UART/physical/simulation/modelsim/work/and1/_primary.dat
UART/physical/simulation/modelsim/work/and1/_primary.vhd
UART/physical/simulation/modelsim/work/and16/verilog.asm
UART/physical/simulation/modelsim/work/and16/_primary.dat
UART/physical/simulation/modelsim/work/and16/_primary.vhd
UART/physical/simulation/modelsim/work/b17mux21/verilog.asm
UART/physical/simulation/modelsim/work/b17mux21/_primary.dat
UART/physical/simulation/modelsim/work/b17mux21/_primary.vhd
UART/physical/simulation/modelsim/work/b5mux21/verilog.asm
UART/physical/simulation/modelsim/work/b5mux21/_primary.dat
UART/physical/simulation/modelsim/work/b5mux21/_primary.vhd
UART/physical/simulation/modelsim/work/bmux21/verilog.asm
UART/physical/simulation/modelsim/work/bmux21/_primary.dat
UART/physical/simulation/modelsim/work/bmux21/_primary.vhd
UART/physical/simulation/modelsim/work/cyclone_asmiblock/verilog.asm
UART/physical/simulation/modelsim/work/cyclone_asmiblock/_primary.dat
UART/physical/simulation/modelsim/work/cyclone_asmiblock/_primary.vhd
UART/physical/simulation/modelsim/work/cyclone_asynch_io/verilog.asm
UART/physical/simulation/modelsim/work/cyclone_asynch_io/_primary.dat
UART/physical/simulation/modelsim/work/cyclone_asynch_io/_primary.vhd
UART/physical/simulation/modelsim/work/cyclone_asynch_lcell/verilog.asm
UART/physical/simulation/modelsim/work/cyclone_asynch_lcell/_primary.dat
UART/physical/simulation/modelsim/work/cyclone_asynch_lcell/_primary.vhd
UART/physical/simulation/modelsim/work/cyclone_crcblock/verilog.asm
UART/physical/simulation/modelsim/work/cyclone_crcblock/_primary.dat
UART/physical/simulation/modelsim/work/cyclone_crcblock/_primary.vhd
UART/physical/simulation/modelsim/work/cyclone_dll/verilog.asm
UART/physical/simulation/modelsim/work/cyclone_d

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