uartram/designer/impl1/designer.log
uartram/designer/impl1/tp_ram_top.adb
uartram/designer/impl1/tp_ram_top.dtf/verify.log
uartram/designer/impl1/tp_ram_top.ide_des
uartram/designer/impl1/tp_ram_top.pdb
uartram/designer/impl1/tp_ram_top.pdb.depends
uartram/designer/impl1/tp_ram_top.tcl
uartram/designer/impl1/tp_ram_top_ba.sdf
uartram/designer/impl1/tp_ram_top_ba.v
uartram/designer/impl1/tp_ram_top_fp/$$FlashPro_09003.L$$
uartram/designer/impl1/tp_ram_top_fp/projectData/tp_ram_top.pdb
uartram/designer/impl1/tp_ram_top_fp/tp_ram_top.log
uartram/designer/impl1/tp_ram_top_fp/tp_ram_top.pro
uartram/hdl/ctrl_ram.v
uartram/hdl/rec.v
uartram/hdl/send.v
uartram/hdl/tp_ram_top.v
uartram/simulation/modelsim.ini
uartram/simulation/t_port_ram_R0C0.mem
uartram/smartgen/smartgen.aws
uartram/smartgen/t_port_ram/t_port_ram.cxf
uartram/smartgen/t_port_ram/t_port_ram.gen
uartram/smartgen/t_port_ram/t_port_ram.log
uartram/smartgen/t_port_ram/t_port_ram.shx
uartram/smartgen/t_port_ram/t_port_ram.v
uartram/smartgen/t_port_ram/t_port_ram_R0C0.mem
uartram/smartgen/t_port_ram_work.ixf
uartram/synthesis/.recordref
uartram/synthesis/run_options.txt
uartram/synthesis/stdout.log
uartram/synthesis/syntmp/sap.log
uartram/synthesis/syntmp/tp_ram_top.msg
uartram/synthesis/syntmp/tp_ram_top.plg
uartram/synthesis/syntmp/tp_ram_top_flink.htm
uartram/synthesis/syntmp/tp_ram_top_srr.htm
uartram/synthesis/syntmp/tp_ram_top_toc.htm
uartram/synthesis/tp_ram_top.areasrr
uartram/synthesis/tp_ram_top.edn
uartram/synthesis/tp_ram_top.fse
uartram/synthesis/tp_ram_top.htm
uartram/synthesis/tp_ram_top.map
uartram/synthesis/tp_ram_top.sap
uartram/synthesis/tp_ram_top.sdf
uartram/synthesis/tp_ram_top.so
uartram/synthesis/tp_ram_top.srd
uartram/synthesis/tp_ram_top.srm
uartram/synthesis/tp_ram_top.srr
uartram/synthesis/tp_ram_top.srs
uartram/synthesis/tp_ram_top.tlg
uartram/synthesis/tp_ram_top_sdc.sdc
uartram/synthesis/tp_ram_top_syn.prj
uartram/synthesis/traplog.tlg
uartram/uartram.prj
uartram/viewdraw/vf/project.lst
uartram/viewdraw/viewdraw.ini
uartram/designer/impl1/tp_ram_top_fp/projectData
uartram/designer/impl1/simulation
uartram/designer/impl1/tp_ram_top.dtf
uartram/designer/impl1/tp_ram_top_fp
uartram/designer/impl1
uartram/smartgen/t_port_ram
uartram/synthesis/backup
uartram/synthesis/syntmp
uartram/viewdraw/sch
uartram/viewdraw/sym
uartram/viewdraw/vf
uartram/viewdraw/wir
uartram/component
uartram/constraint
uartram/coreconsole
uartram/designer
uartram/hdl
uartram/phy_synthesis
uartram/simulation
uartram/smartgen
uartram/stimulus
uartram/synthesis
uartram/viewdraw
uartram