文件名称:dual_portram
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以Proasic3 Startkit开发板为平台,对dualram的应用做了基本介绍。-The ProASIC3 StartKit development board as a platform, on the application of dualram basic.
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下载文件列表
dual_portram/designer/impl1/designer.log
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top/verilog.psm
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top/_primary.dat
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top/_primary.dbs
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top/_primary.vhd
dual_portram/designer/impl1/simulation/postlayout/_info
dual_portram/designer/impl1/tp_ram_top.adb
dual_portram/designer/impl1/tp_ram_top.dtf/verify.log
dual_portram/designer/impl1/tp_ram_top.ide_des
dual_portram/designer/impl1/tp_ram_top.pdb
dual_portram/designer/impl1/tp_ram_top.pdb.depends
dual_portram/designer/impl1/tp_ram_top.tcl
dual_portram/designer/impl1/tp_ram_top_ba.sdf
dual_portram/designer/impl1/tp_ram_top_ba.v
dual_portram/designer/impl1/tp_ram_top_fp/$$FlashPro_09003.L$$
dual_portram/designer/impl1/tp_ram_top_fp/projectData/tp_ram_top.pdb
dual_portram/designer/impl1/tp_ram_top_fp/tp_ram_top.log
dual_portram/designer/impl1/tp_ram_top_fp/tp_ram_top.pro
dual_portram/dual_portram.prj
dual_portram/hdl/ctrl_RAM.v
dual_portram/hdl/rec.v
dual_portram/hdl/send.v
dual_portram/hdl/tp_ram_top.v
dual_portram/simulation/dual_port_ram_R0C0.mem
dual_portram/simulation/dual_port_ram_R0C1.mem
dual_portram/simulation/dual_port_ram_R0C2.mem
dual_portram/simulation/dual_port_ram_R0C3.mem
dual_portram/simulation/modelsim.ini
dual_portram/simulation/modelsim.ini.sav
dual_portram/simulation/modelsim.log
dual_portram/simulation/presynth/ctrl_@r@a@m/verilog.psm
dual_portram/simulation/presynth/ctrl_@r@a@m/_primary.dat
dual_portram/simulation/presynth/ctrl_@r@a@m/_primary.dbs
dual_portram/simulation/presynth/ctrl_@r@a@m/_primary.vhd
dual_portram/simulation/presynth/dual_port_ram/verilog.psm
dual_portram/simulation/presynth/dual_port_ram/_primary.dat
dual_portram/simulation/presynth/dual_port_ram/_primary.dbs
dual_portram/simulation/presynth/dual_port_ram/_primary.vhd
dual_portram/simulation/presynth/rec/verilog.psm
dual_portram/simulation/presynth/rec/_primary.dat
dual_portram/simulation/presynth/rec/_primary.dbs
dual_portram/simulation/presynth/rec/_primary.vhd
dual_portram/simulation/presynth/send/verilog.psm
dual_portram/simulation/presynth/send/_primary.dat
dual_portram/simulation/presynth/send/_primary.dbs
dual_portram/simulation/presynth/send/_primary.vhd
dual_portram/simulation/presynth/tp_ram_top/verilog.psm
dual_portram/simulation/presynth/tp_ram_top/_primary.dat
dual_portram/simulation/presynth/tp_ram_top/_primary.dbs
dual_portram/simulation/presynth/tp_ram_top/_primary.vhd
dual_portram/simulation/presynth/_info
dual_portram/simulation/run.do
dual_portram/simulation/vsim.wlf
dual_portram/smartgen/dual_port_ram/dual_port_ram.cxf
dual_portram/smartgen/dual_port_ram/dual_port_ram.gen
dual_portram/smartgen/dual_port_ram/dual_port_ram.log
dual_portram/smartgen/dual_port_ram/dual_port_ram.shx
dual_portram/smartgen/dual_port_ram/dual_port_ram.v
dual_portram/smartgen/dual_port_ram/dual_port_ram_R0C0.mem
dual_portram/smartgen/dual_port_ram/dual_port_ram_R0C1.mem
dual_portram/smartgen/dual_port_ram/dual_port_ram_R0C2.mem
dual_portram/smartgen/dual_port_ram/dual_port_ram_R0C3.mem
dual_portram/smartgen/dual_port_ram_work.ixf
dual_portram/smartgen/smartgen.aws
dual_portram/synthesis/.recordref
dual_portram/synthesis/backup/tp_ram_top.srr
dual_portram/synthesis/run_options.txt
dual_portram/synthesis/stdout.log
dual_portram/synthesis/syntmp/sap.log
dual_portram/synthesis/syntmp/tp_ram_top.msg
dual_portram/synthesis/syntmp/tp_ram_top.plg
dual_portram/synthesis/syntmp/tp_ram_top_flink.htm
dual_portram/synthesis/syntmp/tp_ram_top_srr.htm
dual_portram/synthesis/syntmp/tp_ram_top_toc.htm
dual_portram/synthesis/tp_ram_top.areasrr
dual_portram/synthesis/tp_ram_top.edn
dual_portram/synthesis/tp_ram_top.fse
dual_portram/synthesis/tp_ram_top.htm
dual_portram/synthesis/tp_ram_top.map
dual_portram/synthesis/tp_ram_top.sap
dual_portram/synthesis/tp_ram_top.sdf
dual_portram/synthesis/tp_ram_top.so
dual_portram/synthesis/tp_ram_top.srd
dual_portram/synthesis/tp_ram_top.srm
dual_portram/synthesis/tp_ram_top.srr
dual_portram/synthesis/tp_ram_top.srs
dual_portram/synthesis/tp_ram_top.tlg
dual_portram/synthesis/tp_ram_top_sdc.sdc
dual_portram/synthesis/tp_ram_top_syn.prd
dual_portram/synthesis/tp_ram_top_syn.prj
dual_portram/synthesis/traplog.tlg
dual_portram/viewdraw/vf/project.lst
dual_portram/viewdraw/viewdraw.ini
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top
dual_portram/designer/impl1/simulation/postlayout/_temp
dual_portram/designer/impl1/simulation/postlayout
dual_portram/designer/impl1/tp_ram_top_fp/projectData
dual_portram/designer/impl1/simulation
dual_portram/designer/impl1/tp_ram_top.dtf
dual_portram/designer/impl1/tp_ram_top_fp
dual_portram/simulation/presynth/ctrl_@r@a@m
dual_portram/simulation/presynth/dual_port_ram
dual_portram/simulation/presynth/rec
dual_portram/simulation/presynth/send
dual_portram/simulation/presynth/tp_ram_top
dual_portram/simulation/presynth/_temp
dual_portram/designer/impl1
dual_portram/simulation/presynth
dual_portram/smartgen/dual_port_ram
dual_portram/synthesis/backup
dual_p
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top/verilog.psm
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top/_primary.dat
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top/_primary.dbs
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top/_primary.vhd
dual_portram/designer/impl1/simulation/postlayout/_info
dual_portram/designer/impl1/tp_ram_top.adb
dual_portram/designer/impl1/tp_ram_top.dtf/verify.log
dual_portram/designer/impl1/tp_ram_top.ide_des
dual_portram/designer/impl1/tp_ram_top.pdb
dual_portram/designer/impl1/tp_ram_top.pdb.depends
dual_portram/designer/impl1/tp_ram_top.tcl
dual_portram/designer/impl1/tp_ram_top_ba.sdf
dual_portram/designer/impl1/tp_ram_top_ba.v
dual_portram/designer/impl1/tp_ram_top_fp/$$FlashPro_09003.L$$
dual_portram/designer/impl1/tp_ram_top_fp/projectData/tp_ram_top.pdb
dual_portram/designer/impl1/tp_ram_top_fp/tp_ram_top.log
dual_portram/designer/impl1/tp_ram_top_fp/tp_ram_top.pro
dual_portram/dual_portram.prj
dual_portram/hdl/ctrl_RAM.v
dual_portram/hdl/rec.v
dual_portram/hdl/send.v
dual_portram/hdl/tp_ram_top.v
dual_portram/simulation/dual_port_ram_R0C0.mem
dual_portram/simulation/dual_port_ram_R0C1.mem
dual_portram/simulation/dual_port_ram_R0C2.mem
dual_portram/simulation/dual_port_ram_R0C3.mem
dual_portram/simulation/modelsim.ini
dual_portram/simulation/modelsim.ini.sav
dual_portram/simulation/modelsim.log
dual_portram/simulation/presynth/ctrl_@r@a@m/verilog.psm
dual_portram/simulation/presynth/ctrl_@r@a@m/_primary.dat
dual_portram/simulation/presynth/ctrl_@r@a@m/_primary.dbs
dual_portram/simulation/presynth/ctrl_@r@a@m/_primary.vhd
dual_portram/simulation/presynth/dual_port_ram/verilog.psm
dual_portram/simulation/presynth/dual_port_ram/_primary.dat
dual_portram/simulation/presynth/dual_port_ram/_primary.dbs
dual_portram/simulation/presynth/dual_port_ram/_primary.vhd
dual_portram/simulation/presynth/rec/verilog.psm
dual_portram/simulation/presynth/rec/_primary.dat
dual_portram/simulation/presynth/rec/_primary.dbs
dual_portram/simulation/presynth/rec/_primary.vhd
dual_portram/simulation/presynth/send/verilog.psm
dual_portram/simulation/presynth/send/_primary.dat
dual_portram/simulation/presynth/send/_primary.dbs
dual_portram/simulation/presynth/send/_primary.vhd
dual_portram/simulation/presynth/tp_ram_top/verilog.psm
dual_portram/simulation/presynth/tp_ram_top/_primary.dat
dual_portram/simulation/presynth/tp_ram_top/_primary.dbs
dual_portram/simulation/presynth/tp_ram_top/_primary.vhd
dual_portram/simulation/presynth/_info
dual_portram/simulation/run.do
dual_portram/simulation/vsim.wlf
dual_portram/smartgen/dual_port_ram/dual_port_ram.cxf
dual_portram/smartgen/dual_port_ram/dual_port_ram.gen
dual_portram/smartgen/dual_port_ram/dual_port_ram.log
dual_portram/smartgen/dual_port_ram/dual_port_ram.shx
dual_portram/smartgen/dual_port_ram/dual_port_ram.v
dual_portram/smartgen/dual_port_ram/dual_port_ram_R0C0.mem
dual_portram/smartgen/dual_port_ram/dual_port_ram_R0C1.mem
dual_portram/smartgen/dual_port_ram/dual_port_ram_R0C2.mem
dual_portram/smartgen/dual_port_ram/dual_port_ram_R0C3.mem
dual_portram/smartgen/dual_port_ram_work.ixf
dual_portram/smartgen/smartgen.aws
dual_portram/synthesis/.recordref
dual_portram/synthesis/backup/tp_ram_top.srr
dual_portram/synthesis/run_options.txt
dual_portram/synthesis/stdout.log
dual_portram/synthesis/syntmp/sap.log
dual_portram/synthesis/syntmp/tp_ram_top.msg
dual_portram/synthesis/syntmp/tp_ram_top.plg
dual_portram/synthesis/syntmp/tp_ram_top_flink.htm
dual_portram/synthesis/syntmp/tp_ram_top_srr.htm
dual_portram/synthesis/syntmp/tp_ram_top_toc.htm
dual_portram/synthesis/tp_ram_top.areasrr
dual_portram/synthesis/tp_ram_top.edn
dual_portram/synthesis/tp_ram_top.fse
dual_portram/synthesis/tp_ram_top.htm
dual_portram/synthesis/tp_ram_top.map
dual_portram/synthesis/tp_ram_top.sap
dual_portram/synthesis/tp_ram_top.sdf
dual_portram/synthesis/tp_ram_top.so
dual_portram/synthesis/tp_ram_top.srd
dual_portram/synthesis/tp_ram_top.srm
dual_portram/synthesis/tp_ram_top.srr
dual_portram/synthesis/tp_ram_top.srs
dual_portram/synthesis/tp_ram_top.tlg
dual_portram/synthesis/tp_ram_top_sdc.sdc
dual_portram/synthesis/tp_ram_top_syn.prd
dual_portram/synthesis/tp_ram_top_syn.prj
dual_portram/synthesis/traplog.tlg
dual_portram/viewdraw/vf/project.lst
dual_portram/viewdraw/viewdraw.ini
dual_portram/designer/impl1/simulation/postlayout/tp_ram_top
dual_portram/designer/impl1/simulation/postlayout/_temp
dual_portram/designer/impl1/simulation/postlayout
dual_portram/designer/impl1/tp_ram_top_fp/projectData
dual_portram/designer/impl1/simulation
dual_portram/designer/impl1/tp_ram_top.dtf
dual_portram/designer/impl1/tp_ram_top_fp
dual_portram/simulation/presynth/ctrl_@r@a@m
dual_portram/simulation/presynth/dual_port_ram
dual_portram/simulation/presynth/rec
dual_portram/simulation/presynth/send
dual_portram/simulation/presynth/tp_ram_top
dual_portram/simulation/presynth/_temp
dual_portram/designer/impl1
dual_portram/simulation/presynth
dual_portram/smartgen/dual_port_ram
dual_portram/synthesis/backup
dual_p
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