文件名称:wishbone2avalone
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由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统
(系统自动生成,下载前可以参看下载内容)
下载文件列表
i2c
i2c/i2c
i2c/i2c/CVS
i2c/i2c/bench
i2c/i2c/bench/CVS
i2c/i2c/bench/verilog
i2c/i2c/bench/verilog/CVS
i2c/i2c/doc
i2c/i2c/doc/CVS
i2c/i2c/doc/src
i2c/i2c/doc/src/CVS
i2c/i2c/documentation
i2c/i2c/documentation/CVS
i2c/i2c/rtl
i2c/i2c/rtl/CVS
i2c/i2c/rtl/verilog
i2c/i2c/rtl/verilog/CVS
i2c/i2c/rtl/vhdl
i2c/i2c/rtl/vhdl/CVS
i2c/i2c/sim
i2c/i2c/sim/CVS
i2c/i2c/sim/i2c_verilog
i2c/i2c/sim/i2c_verilog/CVS
i2c/i2c/sim/i2c_verilog/run
i2c/i2c/sim/i2c_verilog/run/CVS
i2c/i2c/sim/i2c_verilog/run/INCA_libs
i2c/i2c/sim/i2c_verilog/run/INCA_libs/CVS
i2c/i2c/sim/i2c_verilog/run/waves
i2c/i2c/sim/i2c_verilog/run/waves/CVS
i2c/i2c/software
i2c/i2c/software/CVS
i2c/i2c/software/drivers
i2c/i2c/software/drivers/CVS
i2c/i2c/software/include
i2c/i2c/software/include/CVS
i2c/i2c/verilog
i2c/i2c/verilog/CVS
i2c/i2c/vhdl
i2c/i2c/vhdl/CVS
i2c/i2c/CVS/Root
i2c/i2c/CVS/Repository
i2c/i2c/CVS/Entries
i2c/i2c/bench/CVS/Root
i2c/i2c/bench/CVS/Repository
i2c/i2c/bench/CVS/Entries
i2c/i2c/bench/verilog/CVS/Root
i2c/i2c/bench/verilog/CVS/Repository
i2c/i2c/bench/verilog/CVS/Entries
i2c/i2c/bench/verilog/i2c_slave_model.v
i2c/i2c/bench/verilog/spi_slave_model.v
i2c/i2c/bench/verilog/tst_bench_top.v
i2c/i2c/bench/verilog/wb_master_model.v
i2c/i2c/doc/CVS/Root
i2c/i2c/doc/CVS/Repository
i2c/i2c/doc/CVS/Entries
i2c/i2c/doc/i2c_specs.pdf
i2c/i2c/doc/src/CVS/Root
i2c/i2c/doc/src/CVS/Repository
i2c/i2c/doc/src/CVS/Entries
i2c/i2c/documentation/CVS/Root
i2c/i2c/documentation/CVS/Repository
i2c/i2c/documentation/CVS/Entries
i2c/i2c/rtl/CVS/Root
i2c/i2c/rtl/CVS/Repository
i2c/i2c/rtl/CVS/Entries
i2c/i2c/rtl/verilog/CVS/Root
i2c/i2c/rtl/verilog/CVS/Repository
i2c/i2c/rtl/verilog/CVS/Entries
i2c/i2c/rtl/verilog/i2c_master_bit_ctrl.v
i2c/i2c/rtl/verilog/i2c_master_byte_ctrl.v
i2c/i2c/rtl/verilog/i2c_master_defines.v
i2c/i2c/rtl/verilog/i2c_master_top.v
i2c/i2c/rtl/verilog/timescale.v
i2c/i2c/rtl/vhdl/CVS/Root
i2c/i2c/rtl/vhdl/CVS/Repository
i2c/i2c/rtl/vhdl/CVS/Entries
i2c/i2c/rtl/vhdl/I2C.VHD
i2c/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/i2c/rtl/vhdl/i2c_master_top.vhd
i2c/i2c/rtl/vhdl/readme
i2c/i2c/rtl/vhdl/tst_ds1621.vhd
i2c/i2c/sim/CVS/Root
i2c/i2c/sim/CVS/Repository
i2c/i2c/sim/CVS/Entries
i2c/i2c/sim/i2c_verilog/CVS/Root
i2c/i2c/sim/i2c_verilog/CVS/Repository
i2c/i2c/sim/i2c_verilog/CVS/Entries
i2c/i2c/sim/i2c_verilog/run/CVS/Root
i2c/i2c/sim/i2c_verilog/run/CVS/Repository
i2c/i2c/sim/i2c_verilog/run/CVS/Entries
i2c/i2c/sim/i2c_verilog/run/bench.vcd
i2c/i2c/sim/i2c_verilog/run/ncverilog.key
i2c/i2c/sim/i2c_verilog/run/ncverilog.log
i2c/i2c/sim/i2c_verilog/run/run
i2c/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
i2c/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
i2c/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
i2c/i2c/sim/i2c_verilog/run/waves/CVS/Root
i2c/i2c/sim/i2c_verilog/run/waves/CVS/Repository
i2c/i2c/sim/i2c_verilog/run/waves/CVS/Entries
i2c/i2c/software/CVS/Root
i2c/i2c/software/CVS/Repository
i2c/i2c/software/CVS/Entries
i2c/i2c/software/drivers/CVS/Root
i2c/i2c/software/drivers/CVS/Repository
i2c/i2c/software/drivers/CVS/Entries
i2c/i2c/software/include/CVS/Root
i2c/i2c/software/include/CVS/Repository
i2c/i2c/software/include/CVS/Entries
i2c/i2c/software/include/oc_i2c_master.h
i2c/i2c/verilog/CVS/Root
i2c/i2c/verilog/CVS/Repository
i2c/i2c/verilog/CVS/Entries
i2c/i2c/vhdl/CVS/Root
i2c/i2c/vhdl/CVS/Repository
i2c/i2c/vhdl/CVS/Entries
新建 Microsoft Word 文档 (3).doc
www.dssz.com.txt
i2c/i2c
i2c/i2c/CVS
i2c/i2c/bench
i2c/i2c/bench/CVS
i2c/i2c/bench/verilog
i2c/i2c/bench/verilog/CVS
i2c/i2c/doc
i2c/i2c/doc/CVS
i2c/i2c/doc/src
i2c/i2c/doc/src/CVS
i2c/i2c/documentation
i2c/i2c/documentation/CVS
i2c/i2c/rtl
i2c/i2c/rtl/CVS
i2c/i2c/rtl/verilog
i2c/i2c/rtl/verilog/CVS
i2c/i2c/rtl/vhdl
i2c/i2c/rtl/vhdl/CVS
i2c/i2c/sim
i2c/i2c/sim/CVS
i2c/i2c/sim/i2c_verilog
i2c/i2c/sim/i2c_verilog/CVS
i2c/i2c/sim/i2c_verilog/run
i2c/i2c/sim/i2c_verilog/run/CVS
i2c/i2c/sim/i2c_verilog/run/INCA_libs
i2c/i2c/sim/i2c_verilog/run/INCA_libs/CVS
i2c/i2c/sim/i2c_verilog/run/waves
i2c/i2c/sim/i2c_verilog/run/waves/CVS
i2c/i2c/software
i2c/i2c/software/CVS
i2c/i2c/software/drivers
i2c/i2c/software/drivers/CVS
i2c/i2c/software/include
i2c/i2c/software/include/CVS
i2c/i2c/verilog
i2c/i2c/verilog/CVS
i2c/i2c/vhdl
i2c/i2c/vhdl/CVS
i2c/i2c/CVS/Root
i2c/i2c/CVS/Repository
i2c/i2c/CVS/Entries
i2c/i2c/bench/CVS/Root
i2c/i2c/bench/CVS/Repository
i2c/i2c/bench/CVS/Entries
i2c/i2c/bench/verilog/CVS/Root
i2c/i2c/bench/verilog/CVS/Repository
i2c/i2c/bench/verilog/CVS/Entries
i2c/i2c/bench/verilog/i2c_slave_model.v
i2c/i2c/bench/verilog/spi_slave_model.v
i2c/i2c/bench/verilog/tst_bench_top.v
i2c/i2c/bench/verilog/wb_master_model.v
i2c/i2c/doc/CVS/Root
i2c/i2c/doc/CVS/Repository
i2c/i2c/doc/CVS/Entries
i2c/i2c/doc/i2c_specs.pdf
i2c/i2c/doc/src/CVS/Root
i2c/i2c/doc/src/CVS/Repository
i2c/i2c/doc/src/CVS/Entries
i2c/i2c/documentation/CVS/Root
i2c/i2c/documentation/CVS/Repository
i2c/i2c/documentation/CVS/Entries
i2c/i2c/rtl/CVS/Root
i2c/i2c/rtl/CVS/Repository
i2c/i2c/rtl/CVS/Entries
i2c/i2c/rtl/verilog/CVS/Root
i2c/i2c/rtl/verilog/CVS/Repository
i2c/i2c/rtl/verilog/CVS/Entries
i2c/i2c/rtl/verilog/i2c_master_bit_ctrl.v
i2c/i2c/rtl/verilog/i2c_master_byte_ctrl.v
i2c/i2c/rtl/verilog/i2c_master_defines.v
i2c/i2c/rtl/verilog/i2c_master_top.v
i2c/i2c/rtl/verilog/timescale.v
i2c/i2c/rtl/vhdl/CVS/Root
i2c/i2c/rtl/vhdl/CVS/Repository
i2c/i2c/rtl/vhdl/CVS/Entries
i2c/i2c/rtl/vhdl/I2C.VHD
i2c/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/i2c/rtl/vhdl/i2c_master_top.vhd
i2c/i2c/rtl/vhdl/readme
i2c/i2c/rtl/vhdl/tst_ds1621.vhd
i2c/i2c/sim/CVS/Root
i2c/i2c/sim/CVS/Repository
i2c/i2c/sim/CVS/Entries
i2c/i2c/sim/i2c_verilog/CVS/Root
i2c/i2c/sim/i2c_verilog/CVS/Repository
i2c/i2c/sim/i2c_verilog/CVS/Entries
i2c/i2c/sim/i2c_verilog/run/CVS/Root
i2c/i2c/sim/i2c_verilog/run/CVS/Repository
i2c/i2c/sim/i2c_verilog/run/CVS/Entries
i2c/i2c/sim/i2c_verilog/run/bench.vcd
i2c/i2c/sim/i2c_verilog/run/ncverilog.key
i2c/i2c/sim/i2c_verilog/run/ncverilog.log
i2c/i2c/sim/i2c_verilog/run/run
i2c/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
i2c/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
i2c/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
i2c/i2c/sim/i2c_verilog/run/waves/CVS/Root
i2c/i2c/sim/i2c_verilog/run/waves/CVS/Repository
i2c/i2c/sim/i2c_verilog/run/waves/CVS/Entries
i2c/i2c/software/CVS/Root
i2c/i2c/software/CVS/Repository
i2c/i2c/software/CVS/Entries
i2c/i2c/software/drivers/CVS/Root
i2c/i2c/software/drivers/CVS/Repository
i2c/i2c/software/drivers/CVS/Entries
i2c/i2c/software/include/CVS/Root
i2c/i2c/software/include/CVS/Repository
i2c/i2c/software/include/CVS/Entries
i2c/i2c/software/include/oc_i2c_master.h
i2c/i2c/verilog/CVS/Root
i2c/i2c/verilog/CVS/Repository
i2c/i2c/verilog/CVS/Entries
i2c/i2c/vhdl/CVS/Root
i2c/i2c/vhdl/CVS/Repository
i2c/i2c/vhdl/CVS/Entries
新建 Microsoft Word 文档 (3).doc
www.dssz.com.txt
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