文件名称:ddr
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ISE MIG1.6 生成的DDR SDRAM控制器代码(含TESHBENCH)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ddr/ddr.cgp
ddr/mem_interface_top_withtb.xco
ddr/mem_interface_top_withtb_flist.txt
ddr/mem_interface_top_withtb/datasheet.txt
ddr/mem_interface_top_withtb/log.txt
ddr/mem_interface_top_withtb/mig.prj
ddr/mem_interface_top_withtb/mem_interface_top_xmdf.tcl
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_tap_inc.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_idelay_ctrl.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_write_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_rd_wr_addr_fifo_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_ddr_controller_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_path_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_iobs_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_rd_data_fifo_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_user_interface_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_parameters_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_top_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_main_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_wr_data_fifo_16.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_backend_fifos_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_gen_16.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_backend_rom_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_cmp_rd_data_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_controller_iobs_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_v4_dm_iob.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_path_iobs_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_infrastructure_iobs_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_RAM_D_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_pattern_compare8.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_rd_data_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_tap_logic_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_addr_gen_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_v4_dq_iob.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_v4_dqs_iob.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_infrastructure.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_tap_ctrl_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_test_bench_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top.vhd
ddr/mem_interface_top_withtb/sim/ddr.v
ddr/mem_interface_top_withtb/sim/ddr1_test_tb.v
ddr/mem_interface_top_withtb/sim/ddr_parameters.v
ddr/mem_interface_top_withtb/sim/glbl.v
ddr/mem_interface_top_withtb/sim/Readme.txt
ddr/mem_interface_top_withtb/synth/mem_interface_top_dcm_constraints.sdc
ddr/mem_interface_top_withtb/synth/mem_interface_top.sdc
ddr/mem_interface_top_withtb/synth/mem_interface_top.lso
ddr/mem_interface_top_withtb/synth/mem_interface_top.prj
ddr/mem_interface_top_withtb/synth/ddr_v4.sdc
ddr/mem_interface_top_withtb/synth/script.tcl
ddr/mem_interface_top_withtb/docs/read_timingsheet_0.xls
ddr/mem_interface_top_withtb/docs/write_timingsheet_0.xls
ddr/mem_interface_top_withtb/docs/adr_cntrl_timingsheet_0.xls
ddr/mem_interface_top_withtb/docs/xapp709.pdf
ddr/mem_interface_top_withtb/docs/xapp701.pdf
ddr/mem_interface_top_withtb/par/mem_interface_top.ucf
ddr/mem_interface_top_withtb/par/ise_flow.bat
ddr/mem_interface_top_withtb/par/mem_interface_top.ut
ddr/mem_interface_top_withtb/par/README.txt
ddr/mem_interface_top_withtb/par/xst_run.txt
ddr/mem_interface_top_withouttb/datasheet.txt
ddr/mem_interface_top_withouttb/log.txt
ddr/mem_interface_top_withouttb/mig.prj
ddr/mem_interface_top_withouttb/mem_interface_top_xmdf.tcl
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_tap_inc.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_idelay_ctrl.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_write_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_wr_addr_fifo_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_ddr_controller_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_path_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_iobs_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_data_fifo_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_user_interface_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_parameters_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_top_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_wr_data_fifo_16.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_backend_fifos_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_controller_iobs_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_v4_dm_iob.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_path_iobs_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_infrastructure_iobs_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_RAM_D_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_pattern_compare8.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_data_0.vhd
ddr/
ddr/mem_interface_top_withtb.xco
ddr/mem_interface_top_withtb_flist.txt
ddr/mem_interface_top_withtb/datasheet.txt
ddr/mem_interface_top_withtb/log.txt
ddr/mem_interface_top_withtb/mig.prj
ddr/mem_interface_top_withtb/mem_interface_top_xmdf.tcl
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_tap_inc.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_idelay_ctrl.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_write_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_rd_wr_addr_fifo_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_ddr_controller_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_path_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_iobs_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_rd_data_fifo_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_user_interface_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_parameters_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_top_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_main_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_wr_data_fifo_16.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_backend_fifos_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_gen_16.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_backend_rom_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_cmp_rd_data_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_controller_iobs_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_v4_dm_iob.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_data_path_iobs_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_infrastructure_iobs_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_RAM_D_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_pattern_compare8.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_rd_data_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_tap_logic_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_addr_gen_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_v4_dq_iob.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_v4_dqs_iob.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_infrastructure.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_tap_ctrl_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top_test_bench_0.vhd
ddr/mem_interface_top_withtb/rtl/mem_interface_top.vhd
ddr/mem_interface_top_withtb/sim/ddr.v
ddr/mem_interface_top_withtb/sim/ddr1_test_tb.v
ddr/mem_interface_top_withtb/sim/ddr_parameters.v
ddr/mem_interface_top_withtb/sim/glbl.v
ddr/mem_interface_top_withtb/sim/Readme.txt
ddr/mem_interface_top_withtb/synth/mem_interface_top_dcm_constraints.sdc
ddr/mem_interface_top_withtb/synth/mem_interface_top.sdc
ddr/mem_interface_top_withtb/synth/mem_interface_top.lso
ddr/mem_interface_top_withtb/synth/mem_interface_top.prj
ddr/mem_interface_top_withtb/synth/ddr_v4.sdc
ddr/mem_interface_top_withtb/synth/script.tcl
ddr/mem_interface_top_withtb/docs/read_timingsheet_0.xls
ddr/mem_interface_top_withtb/docs/write_timingsheet_0.xls
ddr/mem_interface_top_withtb/docs/adr_cntrl_timingsheet_0.xls
ddr/mem_interface_top_withtb/docs/xapp709.pdf
ddr/mem_interface_top_withtb/docs/xapp701.pdf
ddr/mem_interface_top_withtb/par/mem_interface_top.ucf
ddr/mem_interface_top_withtb/par/ise_flow.bat
ddr/mem_interface_top_withtb/par/mem_interface_top.ut
ddr/mem_interface_top_withtb/par/README.txt
ddr/mem_interface_top_withtb/par/xst_run.txt
ddr/mem_interface_top_withouttb/datasheet.txt
ddr/mem_interface_top_withouttb/log.txt
ddr/mem_interface_top_withouttb/mig.prj
ddr/mem_interface_top_withouttb/mem_interface_top_xmdf.tcl
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_tap_inc.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_idelay_ctrl.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_write_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_wr_addr_fifo_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_ddr_controller_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_path_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_iobs_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_data_fifo_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_user_interface_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_parameters_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_top_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_wr_data_fifo_16.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_backend_fifos_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_controller_iobs_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_v4_dm_iob.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_data_path_iobs_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_infrastructure_iobs_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_RAM_D_0.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_pattern_compare8.vhd
ddr/mem_interface_top_withouttb/rtl/mem_interface_top_rd_data_0.vhd
ddr/
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