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文件名称:count_0

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-05-05
  • 文件大小：
    292.91kb
  • 已下载：
    0次
  • 提 供 者：
    f***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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利用控制器和数据通道组成的连续16bits中两个1之间间隔0个数最大的计数器。包括顶层模块，控制器模块和数据通道模块的Verilog源码和时序仿真波形。-Continuous 16bits using the controller and data path in intervals of two between 1 and 0 of the largest number of counter. Including the top module, controller module and data channel module Verilog source code and simulation waveform.
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下载文件列表

count_0/controller.v
count_0/count_0_num.asm.rpt
count_0/count_0_num.done
count_0/count_0_num.eda.rpt
count_0/count_0_num.fit.eqn
count_0/count_0_num.fit.rpt
count_0/count_0_num.fit.summary
count_0/count_0_num.flow.rpt
count_0/count_0_num.map.eqn
count_0/count_0_num.map.rpt
count_0/count_0_num.map.summary
count_0/count_0_num.pin
count_0/count_0_num.pof
count_0/count_0_num.qpf
count_0/count_0_num.qsf
count_0/count_0_num.qws
count_0/count_0_num.sim.rpt
count_0/count_0_num.sof
count_0/count_0_num.tan.rpt
count_0/count_0_num.tan.summary
count_0/count_0_num.v
count_0/count_0_num.vt
count_0/count_0_num.vwf
count_0/datapath.v
count_0/db/count_0_num.(0).cnf.cdb
count_0/db/count_0_num.(0).cnf.hdb
count_0/db/count_0_num.(1).cnf.cdb
count_0/db/count_0_num.(1).cnf.hdb
count_0/db/count_0_num.(2).cnf.cdb
count_0/db/count_0_num.(2).cnf.hdb
count_0/db/count_0_num.asm.qmsg
count_0/db/count_0_num.asm_labs.ddb
count_0/db/count_0_num.cbx.xml
count_0/db/count_0_num.cmp.cdb
count_0/db/count_0_num.cmp.hdb
count_0/db/count_0_num.cmp.logdb
count_0/db/count_0_num.cmp.qrpt
count_0/db/count_0_num.cmp.rdb
count_0/db/count_0_num.cmp.tdb
count_0/db/count_0_num.cmp0.ddb
count_0/db/count_0_num.dbp
count_0/db/count_0_num.db_info
count_0/db/count_0_num.eco.cdb
count_0/db/count_0_num.eda.qmsg
count_0/db/count_0_num.eds_overflow
count_0/db/count_0_num.fit.qmsg
count_0/db/count_0_num.hier_info
count_0/db/count_0_num.hif
count_0/db/count_0_num.map.cdb
count_0/db/count_0_num.map.hdb
count_0/db/count_0_num.map.logdb
count_0/db/count_0_num.map.qmsg
count_0/db/count_0_num.pre_map.cdb
count_0/db/count_0_num.pre_map.hdb
count_0/db/count_0_num.psp
count_0/db/count_0_num.rtlv.hdb
count_0/db/count_0_num.rtlv_sg.cdb
count_0/db/count_0_num.rtlv_sg_swap.cdb
count_0/db/count_0_num.sgdiff.cdb
count_0/db/count_0_num.sgdiff.hdb
count_0/db/count_0_num.signalprobe.cdb
count_0/db/count_0_num.sim.hdb
count_0/db/count_0_num.sim.qmsg
count_0/db/count_0_num.sim.qrpt
count_0/db/count_0_num.sim.rdb
count_0/db/count_0_num.sim.vwf
count_0/db/count_0_num.sld_design_entry.sci
count_0/db/count_0_num.sld_design_entry_dsc.sci
count_0/db/count_0_num.smp_dump.txt
count_0/db/count_0_num.syn_hier_info
count_0/db/count_0_num.tan.qmsg
count_0/quartus_nativelink_simulation.log
count_0/serv_req_info.txt
count_0/simulation/modelsim/count_0_num.vo
count_0/simulation/modelsim/count_0_num.vt
count_0/simulation/modelsim/count_0_num_modelsim.xrf
count_0/simulation/modelsim/count_0_num_run_msim_gate_verilog.do
count_0/simulation/modelsim/count_0_num_run_msim_gate_verilog.do.bak
count_0/simulation/modelsim/count_0_num_run_msim_gate_verilog.do.bak1
count_0/simulation/modelsim/count_0_num_run_msim_rtl_verilog.do
count_0/simulation/modelsim/count_0_num_run_msim_rtl_verilog.do.bak
count_0/simulation/modelsim/count_0_num_v.sdo
count_0/timing/primetime/count_0_num.vo
count_0/timing/primetime/count_0_num_pt_v.tcl
count_0/timing/primetime/count_0_num_v.sdo
count_0/simulation/modelsim
count_0/timing/primetime
count_0/db
count_0/simulation
count_0/timing
count_0

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