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文件名称:clock1

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  • 上传时间:
    2013-05-10
  • 文件大小:
    3mb
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介绍说明--下载内容来自于网络,使用问题请自行百度

该代码实现的是使用VHDL语言编程实现的FPGA上的时钟分频。通过修改代码中的参数改变FPGA的输出时钟频率。-The code implements the VHDL language programming on the FPGA clock divider. Changed by modifying the parameters in the code of the output clock frequency of the FPGA.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

clock1/
clock1/Project.dhp
clock1/__ISE_repository_clock1.ise_.lock
clock1/__projnav.log
clock1/_impact.cmd
clock1/_impact.log
clock1/_ngo/
clock1/_ngo/netlist.lst
clock1/_pace.ucf
clock1/_xmsgs/
clock1/_xmsgs/bitgen.xmsgs
clock1/_xmsgs/map.xmsgs
clock1/_xmsgs/ngdbuild.xmsgs
clock1/_xmsgs/par.xmsgs
clock1/_xmsgs/trce.xmsgs
clock1/_xmsgs/xst.xmsgs
clock1/automake.log
clock1/bitgen.ut
clock1/clock1.bgn
clock1/clock1.bit
clock1/clock1.bld
clock1/clock1.cmd_log
clock1/clock1.dhp
clock1/clock1.drc
clock1/clock1.ise
clock1/clock1.ise.old
clock1/clock1.ise_ISE_Backup
clock1/clock1.isim_stx_prj
clock1/clock1.isim_stx_sim
clock1/clock1.lfp
clock1/clock1.lso
clock1/clock1.mrp
clock1/clock1.msd
clock1/clock1.msk
clock1/clock1.ncd
clock1/clock1.ngc
clock1/clock1.ngd
clock1/clock1.ngm
clock1/clock1.ngr
clock1/clock1.ntrc_log
clock1/clock1.pad
clock1/clock1.par
clock1/clock1.par_nlf
clock1/clock1.pcf
clock1/clock1.prj
clock1/clock1.rbb
clock1/clock1.rbd
clock1/clock1.restore
clock1/clock1.stx
clock1/clock1.syr
clock1/clock1.twr
clock1/clock1.twx
clock1/clock1.ucf
clock1/clock1.unroutes
clock1/clock1.ut
clock1/clock1.vhd
clock1/clock1.xpi
clock1/clock1.xst
clock1/clock1_guide.ncd
clock1/clock1_ise9migration.zip
clock1/clock1_last_par.ncd
clock1/clock1_map.map
clock1/clock1_map.mrp
clock1/clock1_map.ncd
clock1/clock1_map.ngm
clock1/clock1_pad.csv
clock1/clock1_pad.txt
clock1/clock1_prev_built.ngd
clock1/clock1_stx.prj
clock1/clock1_summary.html
clock1/clock1_summary.xml
clock1/clock1_timesim.nlf
clock1/clock1_timesim.sdf
clock1/clock1_timesim.vhd
clock1/clock1_usage.xml
clock1/clock1_vhdl.prj
clock1/device_usage_statistics.html
clock1/disp.vhd
clock1/drive.vhd
clock1/isim.cmd
clock1/isim.hdlsourcefiles
clock1/isim.tmp_save/
clock1/isim.tmp_save/_1
clock1/isimwavedata.xwv
clock1/math.lso
clock1/math.prj
clock1/math.stx
clock1/math_vhdl.prj
clock1/pepExtractor.prj
clock1/prjname.lso
clock1/simprim.auxlib/
clock1/simprim.auxlib/hdllib.ref
clock1/simprim.auxlib/vcomponents/
clock1/simprim.auxlib/vcomponents/mingw/
clock1/simprim.auxlib/vcomponents/mingw/vcomponents.obj
clock1/simprim.auxlib/vcomponents/vcomponents.h
clock1/simprim.auxlib/vpackage/
clock1/simprim.auxlib/vpackage/mingw/
clock1/simprim.auxlib/vpackage/mingw/vpackage.obj
clock1/simprim.auxlib/vpackage/vpackage.h
clock1/simprim.auxlib/x_and2/
clock1/simprim.auxlib/x_and2/entity.cpp
clock1/simprim.auxlib/x_and2/entity.h
clock1/simprim.auxlib/x_and2/mingw/
clock1/simprim.auxlib/x_and2/mingw/x_and2_v.obj
clock1/simprim.auxlib/x_and2/x_and2_v.h
clock1/simprim.auxlib/x_buf_pp/
clock1/simprim.auxlib/x_buf_pp/entity.cpp
clock1/simprim.auxlib/x_buf_pp/entity.h
clock1/simprim.auxlib/x_buf_pp/mingw/
clock1/simprim.auxlib/x_buf_pp/mingw/x_buf_pp_v.obj
clock1/simprim.auxlib/x_buf_pp/x_buf_pp_v.h
clock1/simprim.auxlib/x_bufgmux/
clock1/simprim.auxlib/x_bufgmux/entity.cpp
clock1/simprim.auxlib/x_bufgmux/entity.h
clock1/simprim.auxlib/x_bufgmux/mingw/
clock1/simprim.auxlib/x_bufgmux/mingw/x_bufgmux_v.obj
clock1/simprim.auxlib/x_bufgmux/x_bufgmux_v.h
clock1/simprim.auxlib/x_ff/
clock1/simprim.auxlib/x_ff/entity.cpp
clock1/simprim.auxlib/x_ff/entity.h
clock1/simprim.auxlib/x_ff/mingw/
clock1/simprim.auxlib/x_ff/mingw/x_ff_v.obj
clock1/simprim.auxlib/x_ff/x_ff_v.h
clock1/simprim.auxlib/x_inv_pp/
clock1/simprim.auxlib/x_inv_pp/entity.cpp
clock1/simprim.auxlib/x_inv_pp/entity.h
clock1/simprim.auxlib/x_inv_pp/mingw/
clock1/simprim.auxlib/x_inv_pp/mingw/x_inv_pp_v.obj
clock1/simprim.auxlib/x_inv_pp/x_inv_pp_v.h
clock1/simprim.auxlib/x_latche/
clock1/simprim.auxlib/x_latche/entity.cpp
clock1/simprim.auxlib/x_latche/entity.h
clock1/simprim.auxlib/x_latche/mingw/
clock1/simprim.auxlib/x_latche/mingw/x_latche_v.obj
clock1/simprim.auxlib/x_latche/x_latche_v.h
clock1/simprim.auxlib/x_lut4/
clock1/simprim.auxlib/x_lut4/entity.cpp
clock1/simprim.auxlib/x_lut4/entity.h
clock1/simprim.auxlib/x_lut4/mingw/
clock1/simprim.auxlib/x_lut4/mingw/x_lut4_v.obj
clock1/simprim.auxlib/x_lut4/x_lut4_v.h
clock1/simprim.auxlib/x_mux2/
clock1/simprim.auxlib/x_mux2/entity.cpp
clock1/simprim.auxlib/x_mux2/entity.h
clock1/simprim.auxlib/x_mux2/mingw/
clock1/simprim.auxlib/x_mux2/mingw/x_mux2_v.obj
clock1/simprim.auxlib/x_mux2/x_mux2_v.h
clock1/simprim.auxlib/x_one/
clock1/simprim.auxlib/x_one/entity.cpp
clock1/simprim.auxlib/x_one/entity.h
clock1/simprim.auxlib/x_one/mingw/
clock1/simprim.auxlib/x_one/mingw/x_one_v.obj
clock1/simprim.auxlib/x_one/x_one_v.h
clock1/simprim.auxlib/x_or2/
clock1/simprim.auxlib/x_or2/entity.cpp
clock1/simprim.auxlib/x_or2/entity.h
clock1/simprim.auxlib/x_or2/mingw/
clock1/simprim.auxlib/x_or2/mingw/x_or2_v.obj
clock1/simprim.auxlib/x_or2/x_or2_v.h
clock1/simprim.auxlib/x_roc/
clock1/simprim.auxlib/x_roc/entity.cpp
clock1/simprim.auxlib/x_roc/entity.h
clock1/simprim.auxlib/x_roc/mingw/
clock1/simprim.auxlib/x_roc/mingw/x_roc_v.obj
clock1/simprim.auxlib/x_roc/x_roc_v.h
clock1/simprim.auxlib/x_sff/
clock1/simprim.auxlib/x_sff/entity.cpp
clock1/simprim.auxlib/x_sff/entity.h
clock1/simprim.auxlib/x_sff/mingw/
clock1/simprim.auxlib/x_sff/mingw/x_sff_v.obj
clock1/simprim.auxlib/x_sff/x_sff_v.h
clock1/simprim.a

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