文件名称:usb1_funct
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USB2.0的IP核(详细verilog源码和文档)-USB2.0 IP core (detailed Verilog source code and documentation)
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下载文件列表
usb1_funct/
usb1_funct/bench/
usb1_funct/bench/CVS/
usb1_funct/bench/CVS/Entries
usb1_funct/bench/CVS/Repository
usb1_funct/bench/CVS/Root
usb1_funct/bench/verilog/
usb1_funct/bench/verilog/CVS/
usb1_funct/bench/verilog/CVS/Entries
usb1_funct/bench/verilog/CVS/Repository
usb1_funct/bench/verilog/CVS/Root
usb1_funct/doc/
usb1_funct/doc/CVS/
usb1_funct/doc/CVS/Entries
usb1_funct/doc/CVS/Repository
usb1_funct/doc/CVS/Root
usb1_funct/doc/README.txt
usb1_funct/doc/STATUS.txt
usb1_funct/doc/usb_doc.pdf
usb1_funct/rtl/
usb1_funct/rtl/CVS/
usb1_funct/rtl/CVS/Entries
usb1_funct/rtl/CVS/Repository
usb1_funct/rtl/CVS/Root
usb1_funct/rtl/verilog/
usb1_funct/rtl/verilog/CVS/
usb1_funct/rtl/verilog/CVS/Entries
usb1_funct/rtl/verilog/CVS/Repository
usb1_funct/rtl/verilog/CVS/Root
usb1_funct/rtl/verilog/usbf_crc16.v
usb1_funct/rtl/verilog/usbf_crc5.v
usb1_funct/rtl/verilog/usbf_defines.v
usb1_funct/rtl/verilog/usbf_ep_rf.v
usb1_funct/rtl/verilog/usbf_ep_rf_dummy.v
usb1_funct/rtl/verilog/usbf_idma.v
usb1_funct/rtl/verilog/usbf_mem_arb.v
usb1_funct/rtl/verilog/usbf_pa.v
usb1_funct/rtl/verilog/usbf_pd.v
usb1_funct/rtl/verilog/usbf_pe.v
usb1_funct/rtl/verilog/usbf_pl.v
usb1_funct/rtl/verilog/usbf_rf.v
usb1_funct/rtl/verilog/usbf_top.v
usb1_funct/rtl/verilog/usbf_utmi_if.v
usb1_funct/rtl/verilog/usbf_utmi_ls.v
usb1_funct/rtl/verilog/usbf_wb.v
usb1_funct/sim/
usb1_funct/sim/CVS/
usb1_funct/sim/CVS/Entries
usb1_funct/sim/CVS/Repository
usb1_funct/sim/CVS/Root
usb1_funct/sim/rtl_sim/
usb1_funct/sim/rtl_sim/CVS/
usb1_funct/sim/rtl_sim/CVS/Entries
usb1_funct/sim/rtl_sim/CVS/Repository
usb1_funct/sim/rtl_sim/CVS/Root
usb1_funct/sim/rtl_sim/bin/
usb1_funct/sim/rtl_sim/bin/CVS/
usb1_funct/sim/rtl_sim/bin/CVS/Entries
usb1_funct/sim/rtl_sim/bin/CVS/Repository
usb1_funct/sim/rtl_sim/bin/CVS/Root
usb1_funct/sim/rtl_sim/run/
usb1_funct/sim/rtl_sim/run/CVS/
usb1_funct/sim/rtl_sim/run/CVS/Entries
usb1_funct/sim/rtl_sim/run/CVS/Repository
usb1_funct/sim/rtl_sim/run/CVS/Root
usb1_funct/syn/
usb1_funct/syn/CVS/
usb1_funct/syn/CVS/Entries
usb1_funct/syn/CVS/Repository
usb1_funct/syn/CVS/Root
usb1_funct/syn/bin/
usb1_funct/syn/bin/CVS/
usb1_funct/syn/bin/CVS/Entries
usb1_funct/syn/bin/CVS/Repository
usb1_funct/syn/bin/CVS/Root
usb1_funct/syn/bin/comp.dc
usb1_funct/syn/bin/design_spec.dc
usb1_funct/syn/bin/lib_spec.dc
usb1_funct/syn/bin/read.dc
usb1_funct/syn/log/
usb1_funct/syn/log/CVS/
usb1_funct/syn/log/CVS/Entries
usb1_funct/syn/log/CVS/Repository
usb1_funct/syn/log/CVS/Root
usb1_funct/syn/out/
usb1_funct/syn/out/CVS/
usb1_funct/syn/out/CVS/Entries
usb1_funct/syn/out/CVS/Repository
usb1_funct/syn/out/CVS/Root
usb1_funct/syn/run/
usb1_funct/syn/run/CVS/
usb1_funct/syn/run/CVS/Entries
usb1_funct/syn/run/CVS/Repository
usb1_funct/syn/run/CVS/Root
usb1_funct/bench/
usb1_funct/bench/CVS/
usb1_funct/bench/CVS/Entries
usb1_funct/bench/CVS/Repository
usb1_funct/bench/CVS/Root
usb1_funct/bench/verilog/
usb1_funct/bench/verilog/CVS/
usb1_funct/bench/verilog/CVS/Entries
usb1_funct/bench/verilog/CVS/Repository
usb1_funct/bench/verilog/CVS/Root
usb1_funct/doc/
usb1_funct/doc/CVS/
usb1_funct/doc/CVS/Entries
usb1_funct/doc/CVS/Repository
usb1_funct/doc/CVS/Root
usb1_funct/doc/README.txt
usb1_funct/doc/STATUS.txt
usb1_funct/doc/usb_doc.pdf
usb1_funct/rtl/
usb1_funct/rtl/CVS/
usb1_funct/rtl/CVS/Entries
usb1_funct/rtl/CVS/Repository
usb1_funct/rtl/CVS/Root
usb1_funct/rtl/verilog/
usb1_funct/rtl/verilog/CVS/
usb1_funct/rtl/verilog/CVS/Entries
usb1_funct/rtl/verilog/CVS/Repository
usb1_funct/rtl/verilog/CVS/Root
usb1_funct/rtl/verilog/usbf_crc16.v
usb1_funct/rtl/verilog/usbf_crc5.v
usb1_funct/rtl/verilog/usbf_defines.v
usb1_funct/rtl/verilog/usbf_ep_rf.v
usb1_funct/rtl/verilog/usbf_ep_rf_dummy.v
usb1_funct/rtl/verilog/usbf_idma.v
usb1_funct/rtl/verilog/usbf_mem_arb.v
usb1_funct/rtl/verilog/usbf_pa.v
usb1_funct/rtl/verilog/usbf_pd.v
usb1_funct/rtl/verilog/usbf_pe.v
usb1_funct/rtl/verilog/usbf_pl.v
usb1_funct/rtl/verilog/usbf_rf.v
usb1_funct/rtl/verilog/usbf_top.v
usb1_funct/rtl/verilog/usbf_utmi_if.v
usb1_funct/rtl/verilog/usbf_utmi_ls.v
usb1_funct/rtl/verilog/usbf_wb.v
usb1_funct/sim/
usb1_funct/sim/CVS/
usb1_funct/sim/CVS/Entries
usb1_funct/sim/CVS/Repository
usb1_funct/sim/CVS/Root
usb1_funct/sim/rtl_sim/
usb1_funct/sim/rtl_sim/CVS/
usb1_funct/sim/rtl_sim/CVS/Entries
usb1_funct/sim/rtl_sim/CVS/Repository
usb1_funct/sim/rtl_sim/CVS/Root
usb1_funct/sim/rtl_sim/bin/
usb1_funct/sim/rtl_sim/bin/CVS/
usb1_funct/sim/rtl_sim/bin/CVS/Entries
usb1_funct/sim/rtl_sim/bin/CVS/Repository
usb1_funct/sim/rtl_sim/bin/CVS/Root
usb1_funct/sim/rtl_sim/run/
usb1_funct/sim/rtl_sim/run/CVS/
usb1_funct/sim/rtl_sim/run/CVS/Entries
usb1_funct/sim/rtl_sim/run/CVS/Repository
usb1_funct/sim/rtl_sim/run/CVS/Root
usb1_funct/syn/
usb1_funct/syn/CVS/
usb1_funct/syn/CVS/Entries
usb1_funct/syn/CVS/Repository
usb1_funct/syn/CVS/Root
usb1_funct/syn/bin/
usb1_funct/syn/bin/CVS/
usb1_funct/syn/bin/CVS/Entries
usb1_funct/syn/bin/CVS/Repository
usb1_funct/syn/bin/CVS/Root
usb1_funct/syn/bin/comp.dc
usb1_funct/syn/bin/design_spec.dc
usb1_funct/syn/bin/lib_spec.dc
usb1_funct/syn/bin/read.dc
usb1_funct/syn/log/
usb1_funct/syn/log/CVS/
usb1_funct/syn/log/CVS/Entries
usb1_funct/syn/log/CVS/Repository
usb1_funct/syn/log/CVS/Root
usb1_funct/syn/out/
usb1_funct/syn/out/CVS/
usb1_funct/syn/out/CVS/Entries
usb1_funct/syn/out/CVS/Repository
usb1_funct/syn/out/CVS/Root
usb1_funct/syn/run/
usb1_funct/syn/run/CVS/
usb1_funct/syn/run/CVS/Entries
usb1_funct/syn/run/CVS/Repository
usb1_funct/syn/run/CVS/Root
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