文件名称:VHDL
-
所属分类:
- 标签属性:
- 上传时间:2013-05-15
-
文件大小:9.26mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
verilog程序包 包括数码管显示 lcd 红外线接收和读取 -Verilog package includes digital display lcd infrared receiver and read
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VHDL/
VHDL/EX00/
VHDL/EX00/BNT/
VHDL/EX00/BNT/BNT.asm.rpt
VHDL/EX00/BNT/BNT.cdf
VHDL/EX00/BNT/BNT.done
VHDL/EX00/BNT/BNT.dpf
VHDL/EX00/BNT/BNT.fit.rpt
VHDL/EX00/BNT/BNT.fit.smsg
VHDL/EX00/BNT/BNT.fit.summary
VHDL/EX00/BNT/BNT.flow.rpt
VHDL/EX00/BNT/BNT.map.rpt
VHDL/EX00/BNT/BNT.map.summary
VHDL/EX00/BNT/BNT.pin
VHDL/EX00/BNT/BNT.pof
VHDL/EX00/BNT/BNT.qpf
VHDL/EX00/BNT/BNT.qsf
VHDL/EX00/BNT/BNT.qws
VHDL/EX00/BNT/BNT.tan.rpt
VHDL/EX00/BNT/BNT.tan.summary
VHDL/EX00/BNT/BNT.vhd
VHDL/EX00/BNT/BNT.vhd.bak
VHDL/EX00/BNT/db/
VHDL/EX00/BNT/db/BNT.(0).cnf.cdb
VHDL/EX00/BNT/db/BNT.(0).cnf.hdb
VHDL/EX00/BNT/db/BNT.asm.qmsg
VHDL/EX00/BNT/db/BNT.asm_labs.ddb
VHDL/EX00/BNT/db/BNT.cbx.xml
VHDL/EX00/BNT/db/BNT.cmp.cdb
VHDL/EX00/BNT/db/BNT.cmp.hdb
VHDL/EX00/BNT/db/BNT.cmp.logdb
VHDL/EX00/BNT/db/BNT.cmp.rdb
VHDL/EX00/BNT/db/BNT.cmp.tdb
VHDL/EX00/BNT/db/BNT.cmp0.ddb
VHDL/EX00/BNT/db/BNT.dbp
VHDL/EX00/BNT/db/BNT.db_info
VHDL/EX00/BNT/db/BNT.eco.cdb
VHDL/EX00/BNT/db/BNT.fit.qmsg
VHDL/EX00/BNT/db/BNT.hier_info
VHDL/EX00/BNT/db/BNT.hif
VHDL/EX00/BNT/db/BNT.map.cdb
VHDL/EX00/BNT/db/BNT.map.hdb
VHDL/EX00/BNT/db/BNT.map.logdb
VHDL/EX00/BNT/db/BNT.map.qmsg
VHDL/EX00/BNT/db/BNT.pre_map.cdb
VHDL/EX00/BNT/db/BNT.pre_map.hdb
VHDL/EX00/BNT/db/BNT.psp
VHDL/EX00/BNT/db/BNT.pss
VHDL/EX00/BNT/db/BNT.rtlv.hdb
VHDL/EX00/BNT/db/BNT.rtlv_sg.cdb
VHDL/EX00/BNT/db/BNT.rtlv_sg_swap.cdb
VHDL/EX00/BNT/db/BNT.sgdiff.cdb
VHDL/EX00/BNT/db/BNT.sgdiff.hdb
VHDL/EX00/BNT/db/BNT.signalprobe.cdb
VHDL/EX00/BNT/db/BNT.sld_design_entry.sci
VHDL/EX00/BNT/db/BNT.sld_design_entry_dsc.sci
VHDL/EX00/BNT/db/BNT.syn_hier_info
VHDL/EX00/BNT/db/BNT.tan.qmsg
VHDL/EX00/BNT/db/BNT.tis_db_list.ddb
VHDL/EX00/BNT/db/prev_cmp_BNT.map.qmsg
VHDL/EX00/BNT/db/prev_cmp_BNT.qmsg
VHDL/EX00/BNT/MAXII240_570T100C5N_PIN.tcl
VHDL/EX01/
VHDL/EX01/CLK_DIV/
VHDL/EX01/CLK_DIV/CLK_DIV.asm.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.cdf
VHDL/EX01/CLK_DIV/CLK_DIV.done
VHDL/EX01/CLK_DIV/CLK_DIV.dpf
VHDL/EX01/CLK_DIV/CLK_DIV.fit.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.fit.smsg
VHDL/EX01/CLK_DIV/CLK_DIV.fit.summary
VHDL/EX01/CLK_DIV/CLK_DIV.flow.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.map.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.map.summary
VHDL/EX01/CLK_DIV/CLK_DIV.pin
VHDL/EX01/CLK_DIV/CLK_DIV.pof
VHDL/EX01/CLK_DIV/CLK_DIV.qpf
VHDL/EX01/CLK_DIV/CLK_DIV.qsf
VHDL/EX01/CLK_DIV/CLK_DIV.qws
VHDL/EX01/CLK_DIV/CLK_DIV.tan.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.tan.summary
VHDL/EX01/CLK_DIV/CLK_DIV.vhd
VHDL/EX01/CLK_DIV/db/
VHDL/EX01/CLK_DIV/db/CLK_DIV.(0).cnf.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.(0).cnf.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.asm.qmsg
VHDL/EX01/CLK_DIV/db/CLK_DIV.asm_labs.ddb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cbx.xml
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.logdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.rdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.tdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp0.ddb
VHDL/EX01/CLK_DIV/db/CLK_DIV.dbp
VHDL/EX01/CLK_DIV/db/CLK_DIV.db_info
VHDL/EX01/CLK_DIV/db/CLK_DIV.eco.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.fit.qmsg
VHDL/EX01/CLK_DIV/db/CLK_DIV.hier_info
VHDL/EX01/CLK_DIV/db/CLK_DIV.hif
VHDL/EX01/CLK_DIV/db/CLK_DIV.map.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.map.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.map.logdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.map.qmsg
VHDL/EX01/CLK_DIV/db/CLK_DIV.pre_map.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.pre_map.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.psp
VHDL/EX01/CLK_DIV/db/CLK_DIV.pss
VHDL/EX01/CLK_DIV/db/CLK_DIV.rtlv.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.rtlv_sg.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.rtlv_sg_swap.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.sgdiff.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.sgdiff.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.signalprobe.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.sld_design_entry.sci
VHDL/EX01/CLK_DIV/db/CLK_DIV.sld_design_entry_dsc.sci
VHDL/EX01/CLK_DIV/db/CLK_DIV.syn_hier_info
VHDL/EX01/CLK_DIV/db/CLK_DIV.tan.qmsg
VHDL/EX01/CLK_DIV/db/CLK_DIV.tis_db_list.ddb
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.asm.qmsg
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.fit.qmsg
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.map.qmsg
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.qmsg
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.tan.qmsg
VHDL/EX01/CLK_DIV/MAXII240_570T100C5N_PIN.tcl
VHDL/EX01/CLK_DIV/说明.txt
VHDL/EX02/
VHDL/EX02/LED_Flash/
VHDL/EX02/LED_Flash/db/
VHDL/EX02/LED_Flash/db/LED_FLASH.(0).cnf.cdb
VHDL/EX02/LED_Flash/db/LED_FLASH.(0).cnf.hdb
VHDL/EX02/LED_Flash/db/LED_FLASH.asm.qmsg
VHDL/EX02/LED_Flash/db/LED_FLASH.asm_labs.ddb
VHDL/EX02/LED_Flash/db/LED_FLASH.cbx.xml
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.cdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.hdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.logdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.rdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.tdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp0.ddb
VHDL/EX02/LED_Flash/db/LED_FLASH.dbp
VHDL/EX02/LED_Flash/db/LED_FLASH.db_info
VHDL/EX02/LED_Flash/db/LED_FLASH.eco.cdb
VHDL/EX02/LED_Flash/db/LED_FLASH.fit.qmsg
VHDL/EX02/LED_Flash/db/LED_FLASH.hier_info
VHDL/EX02/LED_Flash/db/LED_FLASH.hif
VHDL/EX02/LED_Flash/db/LED_FLASH.map.cdb
VHDL/EX02/LED_Flash/db/LED_FLASH.map.hdb
VHDL/EX02/LED_Flash/db/LED_FLASH.map.logdb
VHDL/EX02/LED_Flash/db/LED_FLASH.map.qmsg
VHDL/EX02/LED_Flash/db/LED_FLASH.pre_map.cdb
VHDL/EX
VHDL/EX00/
VHDL/EX00/BNT/
VHDL/EX00/BNT/BNT.asm.rpt
VHDL/EX00/BNT/BNT.cdf
VHDL/EX00/BNT/BNT.done
VHDL/EX00/BNT/BNT.dpf
VHDL/EX00/BNT/BNT.fit.rpt
VHDL/EX00/BNT/BNT.fit.smsg
VHDL/EX00/BNT/BNT.fit.summary
VHDL/EX00/BNT/BNT.flow.rpt
VHDL/EX00/BNT/BNT.map.rpt
VHDL/EX00/BNT/BNT.map.summary
VHDL/EX00/BNT/BNT.pin
VHDL/EX00/BNT/BNT.pof
VHDL/EX00/BNT/BNT.qpf
VHDL/EX00/BNT/BNT.qsf
VHDL/EX00/BNT/BNT.qws
VHDL/EX00/BNT/BNT.tan.rpt
VHDL/EX00/BNT/BNT.tan.summary
VHDL/EX00/BNT/BNT.vhd
VHDL/EX00/BNT/BNT.vhd.bak
VHDL/EX00/BNT/db/
VHDL/EX00/BNT/db/BNT.(0).cnf.cdb
VHDL/EX00/BNT/db/BNT.(0).cnf.hdb
VHDL/EX00/BNT/db/BNT.asm.qmsg
VHDL/EX00/BNT/db/BNT.asm_labs.ddb
VHDL/EX00/BNT/db/BNT.cbx.xml
VHDL/EX00/BNT/db/BNT.cmp.cdb
VHDL/EX00/BNT/db/BNT.cmp.hdb
VHDL/EX00/BNT/db/BNT.cmp.logdb
VHDL/EX00/BNT/db/BNT.cmp.rdb
VHDL/EX00/BNT/db/BNT.cmp.tdb
VHDL/EX00/BNT/db/BNT.cmp0.ddb
VHDL/EX00/BNT/db/BNT.dbp
VHDL/EX00/BNT/db/BNT.db_info
VHDL/EX00/BNT/db/BNT.eco.cdb
VHDL/EX00/BNT/db/BNT.fit.qmsg
VHDL/EX00/BNT/db/BNT.hier_info
VHDL/EX00/BNT/db/BNT.hif
VHDL/EX00/BNT/db/BNT.map.cdb
VHDL/EX00/BNT/db/BNT.map.hdb
VHDL/EX00/BNT/db/BNT.map.logdb
VHDL/EX00/BNT/db/BNT.map.qmsg
VHDL/EX00/BNT/db/BNT.pre_map.cdb
VHDL/EX00/BNT/db/BNT.pre_map.hdb
VHDL/EX00/BNT/db/BNT.psp
VHDL/EX00/BNT/db/BNT.pss
VHDL/EX00/BNT/db/BNT.rtlv.hdb
VHDL/EX00/BNT/db/BNT.rtlv_sg.cdb
VHDL/EX00/BNT/db/BNT.rtlv_sg_swap.cdb
VHDL/EX00/BNT/db/BNT.sgdiff.cdb
VHDL/EX00/BNT/db/BNT.sgdiff.hdb
VHDL/EX00/BNT/db/BNT.signalprobe.cdb
VHDL/EX00/BNT/db/BNT.sld_design_entry.sci
VHDL/EX00/BNT/db/BNT.sld_design_entry_dsc.sci
VHDL/EX00/BNT/db/BNT.syn_hier_info
VHDL/EX00/BNT/db/BNT.tan.qmsg
VHDL/EX00/BNT/db/BNT.tis_db_list.ddb
VHDL/EX00/BNT/db/prev_cmp_BNT.map.qmsg
VHDL/EX00/BNT/db/prev_cmp_BNT.qmsg
VHDL/EX00/BNT/MAXII240_570T100C5N_PIN.tcl
VHDL/EX01/
VHDL/EX01/CLK_DIV/
VHDL/EX01/CLK_DIV/CLK_DIV.asm.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.cdf
VHDL/EX01/CLK_DIV/CLK_DIV.done
VHDL/EX01/CLK_DIV/CLK_DIV.dpf
VHDL/EX01/CLK_DIV/CLK_DIV.fit.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.fit.smsg
VHDL/EX01/CLK_DIV/CLK_DIV.fit.summary
VHDL/EX01/CLK_DIV/CLK_DIV.flow.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.map.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.map.summary
VHDL/EX01/CLK_DIV/CLK_DIV.pin
VHDL/EX01/CLK_DIV/CLK_DIV.pof
VHDL/EX01/CLK_DIV/CLK_DIV.qpf
VHDL/EX01/CLK_DIV/CLK_DIV.qsf
VHDL/EX01/CLK_DIV/CLK_DIV.qws
VHDL/EX01/CLK_DIV/CLK_DIV.tan.rpt
VHDL/EX01/CLK_DIV/CLK_DIV.tan.summary
VHDL/EX01/CLK_DIV/CLK_DIV.vhd
VHDL/EX01/CLK_DIV/db/
VHDL/EX01/CLK_DIV/db/CLK_DIV.(0).cnf.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.(0).cnf.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.asm.qmsg
VHDL/EX01/CLK_DIV/db/CLK_DIV.asm_labs.ddb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cbx.xml
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.logdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.rdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp.tdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.cmp0.ddb
VHDL/EX01/CLK_DIV/db/CLK_DIV.dbp
VHDL/EX01/CLK_DIV/db/CLK_DIV.db_info
VHDL/EX01/CLK_DIV/db/CLK_DIV.eco.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.fit.qmsg
VHDL/EX01/CLK_DIV/db/CLK_DIV.hier_info
VHDL/EX01/CLK_DIV/db/CLK_DIV.hif
VHDL/EX01/CLK_DIV/db/CLK_DIV.map.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.map.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.map.logdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.map.qmsg
VHDL/EX01/CLK_DIV/db/CLK_DIV.pre_map.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.pre_map.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.psp
VHDL/EX01/CLK_DIV/db/CLK_DIV.pss
VHDL/EX01/CLK_DIV/db/CLK_DIV.rtlv.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.rtlv_sg.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.rtlv_sg_swap.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.sgdiff.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.sgdiff.hdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.signalprobe.cdb
VHDL/EX01/CLK_DIV/db/CLK_DIV.sld_design_entry.sci
VHDL/EX01/CLK_DIV/db/CLK_DIV.sld_design_entry_dsc.sci
VHDL/EX01/CLK_DIV/db/CLK_DIV.syn_hier_info
VHDL/EX01/CLK_DIV/db/CLK_DIV.tan.qmsg
VHDL/EX01/CLK_DIV/db/CLK_DIV.tis_db_list.ddb
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.asm.qmsg
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.fit.qmsg
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.map.qmsg
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.qmsg
VHDL/EX01/CLK_DIV/db/prev_cmp_CLK_DIV.tan.qmsg
VHDL/EX01/CLK_DIV/MAXII240_570T100C5N_PIN.tcl
VHDL/EX01/CLK_DIV/说明.txt
VHDL/EX02/
VHDL/EX02/LED_Flash/
VHDL/EX02/LED_Flash/db/
VHDL/EX02/LED_Flash/db/LED_FLASH.(0).cnf.cdb
VHDL/EX02/LED_Flash/db/LED_FLASH.(0).cnf.hdb
VHDL/EX02/LED_Flash/db/LED_FLASH.asm.qmsg
VHDL/EX02/LED_Flash/db/LED_FLASH.asm_labs.ddb
VHDL/EX02/LED_Flash/db/LED_FLASH.cbx.xml
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.cdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.hdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.logdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.rdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp.tdb
VHDL/EX02/LED_Flash/db/LED_FLASH.cmp0.ddb
VHDL/EX02/LED_Flash/db/LED_FLASH.dbp
VHDL/EX02/LED_Flash/db/LED_FLASH.db_info
VHDL/EX02/LED_Flash/db/LED_FLASH.eco.cdb
VHDL/EX02/LED_Flash/db/LED_FLASH.fit.qmsg
VHDL/EX02/LED_Flash/db/LED_FLASH.hier_info
VHDL/EX02/LED_Flash/db/LED_FLASH.hif
VHDL/EX02/LED_Flash/db/LED_FLASH.map.cdb
VHDL/EX02/LED_Flash/db/LED_FLASH.map.hdb
VHDL/EX02/LED_Flash/db/LED_FLASH.map.logdb
VHDL/EX02/LED_Flash/db/LED_FLASH.map.qmsg
VHDL/EX02/LED_Flash/db/LED_FLASH.pre_map.cdb
VHDL/EX
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.