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文件名称:PipelineCPU

  • 所属分类：
    ARM-PowerPC-ColdFire-MIPS
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-05-18
  • 文件大小：
    10.83mb
  • 已下载：
    1次
  • 提 供 者：
    武****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

这是我们设计的一个MIPS流水线CPU，基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于，5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型，这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句，从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU differences that each of the five pipeline stages maintenance a variable (SelType) indicates that the currently executing instruction types, this treatment data Adventure loaduse adventure or jump adventure when each segment can know The statement is being processed, in order to facilitate our processing.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

PipelineCPU/ALU.v
PipelineCPU/db/add_sub_gvd.tdf
PipelineCPU/db/altsyncram_2rc1.tdf
PipelineCPU/db/altsyncram_9g31.tdf
PipelineCPU/db/altsyncram_a981.tdf
PipelineCPU/db/altsyncram_eb01.tdf
PipelineCPU/db/altsyncram_g981.tdf
PipelineCPU/db/altsyncram_sng1.tdf
PipelineCPU/db/cmpr_6cc.tdf
PipelineCPU/db/cntr_ikf.tdf
PipelineCPU/db/cntr_kkf.tdf
PipelineCPU/db/logic_util_heursitic.dat
PipelineCPU/db/mux_dqc.tdf
PipelineCPU/db/mux_ioc.tdf
PipelineCPU/db/mux_joc.tdf
PipelineCPU/db/PipelineCPU.(0).cnf.cdb
PipelineCPU/db/PipelineCPU.(0).cnf.hdb
PipelineCPU/db/PipelineCPU.(1).cnf.cdb
PipelineCPU/db/PipelineCPU.(1).cnf.hdb
PipelineCPU/db/PipelineCPU.(10).cnf.cdb
PipelineCPU/db/PipelineCPU.(10).cnf.hdb
PipelineCPU/db/PipelineCPU.(2).cnf.cdb
PipelineCPU/db/PipelineCPU.(2).cnf.hdb
PipelineCPU/db/PipelineCPU.(3).cnf.cdb
PipelineCPU/db/PipelineCPU.(3).cnf.hdb
PipelineCPU/db/PipelineCPU.(4).cnf.cdb
PipelineCPU/db/PipelineCPU.(4).cnf.hdb
PipelineCPU/db/PipelineCPU.(5).cnf.cdb
PipelineCPU/db/PipelineCPU.(5).cnf.hdb
PipelineCPU/db/PipelineCPU.(6).cnf.cdb
PipelineCPU/db/PipelineCPU.(6).cnf.hdb
PipelineCPU/db/PipelineCPU.(7).cnf.cdb
PipelineCPU/db/PipelineCPU.(7).cnf.hdb
PipelineCPU/db/PipelineCPU.(8).cnf.cdb
PipelineCPU/db/PipelineCPU.(8).cnf.hdb
PipelineCPU/db/PipelineCPU.(9).cnf.cdb
PipelineCPU/db/PipelineCPU.(9).cnf.hdb
PipelineCPU/db/PipelineCPU.cbx.xml
PipelineCPU/db/PipelineCPU.cmp.rdb
PipelineCPU/db/PipelineCPU.cmp_merge.kpt
PipelineCPU/db/PipelineCPU.db_info
PipelineCPU/db/PipelineCPU.eco.cdb
PipelineCPU/db/PipelineCPU.eds_overflow
PipelineCPU/db/PipelineCPU.fnsim.cdb
PipelineCPU/db/PipelineCPU.fnsim.hdb
PipelineCPU/db/PipelineCPU.fnsim.qmsg
PipelineCPU/db/PipelineCPU.hier_info
PipelineCPU/db/PipelineCPU.hif
PipelineCPU/db/PipelineCPU.lpc.html
PipelineCPU/db/PipelineCPU.lpc.rdb
PipelineCPU/db/PipelineCPU.lpc.txt
PipelineCPU/db/PipelineCPU.map.bpm
PipelineCPU/db/PipelineCPU.map.cdb
PipelineCPU/db/PipelineCPU.map.ecobp
PipelineCPU/db/PipelineCPU.map.hdb
PipelineCPU/db/PipelineCPU.map.kpt
PipelineCPU/db/PipelineCPU.map.logdb
PipelineCPU/db/PipelineCPU.map.qmsg
PipelineCPU/db/PipelineCPU.map_bb.cdb
PipelineCPU/db/PipelineCPU.map_bb.hdb
PipelineCPU/db/PipelineCPU.map_bb.logdb
PipelineCPU/db/PipelineCPU.PipelineCPU0.rtl.mif
PipelineCPU/db/PipelineCPU.pre_map.cdb
PipelineCPU/db/PipelineCPU.pre_map.hdb
PipelineCPU/db/PipelineCPU.rtlv.hdb
PipelineCPU/db/PipelineCPU.rtlv_sg.cdb
PipelineCPU/db/PipelineCPU.rtlv_sg_swap.cdb
PipelineCPU/db/PipelineCPU.sgdiff.cdb
PipelineCPU/db/PipelineCPU.sgdiff.hdb
PipelineCPU/db/PipelineCPU.sim.cvwf
PipelineCPU/db/PipelineCPU.sim.hdb
PipelineCPU/db/PipelineCPU.sim.qmsg
PipelineCPU/db/PipelineCPU.sim.rdb
PipelineCPU/db/PipelineCPU.simfam
PipelineCPU/db/PipelineCPU.sld_design_entry.sci
PipelineCPU/db/PipelineCPU.sld_design_entry_dsc.sci
PipelineCPU/db/PipelineCPU.syn_hier_info
PipelineCPU/db/PipelineCPU.tis_db_list.ddb
PipelineCPU/db/PipelineCPU.tmw_info
PipelineCPU/db/prev_cmp_PipelineCPU.map.qmsg
PipelineCPU/db/prev_cmp_PipelineCPU.qmsg
PipelineCPU/db/prev_cmp_PipelineCPU.sim.qmsg
PipelineCPU/db/shift_taps_m1m.tdf
PipelineCPU/db/shift_taps_q1m.tdf
PipelineCPU/db/shift_taps_t1m.tdf
PipelineCPU/db/wed.wsf
PipelineCPU/Imem.v
PipelineCPU/Imem.v.bak
PipelineCPU/incremental_db/compiled_partitions/PipelineCPU.root_partition.map.atm
PipelineCPU/incremental_db/compiled_partitions/PipelineCPU.root_partition.map.cdb
PipelineCPU/incremental_db/compiled_partitions/PipelineCPU.root_partition.map.dpi
PipelineCPU/incremental_db/compiled_partitions/PipelineCPU.root_partition.map.hdb
PipelineCPU/incremental_db/compiled_partitions/PipelineCPU.root_partition.map.hdbx
PipelineCPU/incremental_db/compiled_partitions/PipelineCPU.root_partition.map.kpt
PipelineCPU/incremental_db/README
PipelineCPU/left2.v
PipelineCPU/left2.v.bak
PipelineCPU/memory.v
PipelineCPU/memory.v.bak
PipelineCPU/PipelineCPU.qpf
PipelineCPU/PipelineCPU.qsf
PipelineCPU/PipelineCPU.qws
PipelineCPU/PipelineCPU.rar
PipelineCPU/PipelineCPU.v
PipelineCPU/PipelineCPU.v.bak
PipelineCPU/PipelineCPU.vwf
PipelineCPU/PLUS.v
PipelineCPU/PLUS.v.bak
PipelineCPU/register.v
PipelineCPU/register.v.bak
PipelineCPU/release/PipelineCPU.done
PipelineCPU/release/PipelineCPU.flow.rpt
PipelineCPU/release/PipelineCPU.map.rpt
PipelineCPU/release/PipelineCPU.map.smsg
PipelineCPU/release/PipelineCPU.map.summary
PipelineCPU/release/PipelineCPU.sim.rpt
PipelineCPU/Shift.v
PipelineCPU/signedextend.v
PipelineCPU/incremental_db/compiled_partitions
PipelineCPU/db
PipelineCPU/incremental_db
PipelineCPU/release
PipelineCPU

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