A 20-GHz low noise amplifier (LNA) is designed in 0.13 CMOS technology. The proposed amplifier employs twocascade stages to achieve a peak power-gain of 25 dB and a noisefigure of 4.8 dB at 20.4 GHz. The power consumption of the LNA

circuit is 12.2 mW from a 1.5V supply. This paper also presents a

novel model for sub-nH planar spiral inductors, which accounts

for high-frequency effects and incorporates interconnection lines

in the 1.5-turn spiral inductor. The new model demonstrates a

good agreement with S-parameter from electromagnetic field

simulator within 40GHz.-A 20-GHz low noise amplifier (LNA) is designed in

0.13􀈝 􀁐 􀀃 CMOS technology. The proposed amplifier employs two

cascade stages to achieve a peak power-gain of 25 dB and a noise

figure of 4.8 dB at 20.4 GHz. The power consumption of the LNA

circuit is 12.2 mW from a 1.5V supply. This paper also presents a

novel model for sub-nH planar spiral inductors, which accounts

for high-frequency effects and incorporates interconnection lines

in the 1.5-turn spiral inductor. The new model demonstrates a

good agreement with S-parameter from electromagnetic field

simulator within 40GHz.