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文件名称:Digital_Clock

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  • 上传时间:
    2013-05-20
  • 文件大小:
    582.24kb
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FPGA数字时钟完美通过测试。目标板是ZRTECH的EP2C5T144C8 CORE2-5U核心板及PERI1-8KD配套子卡。-The FPGA digital clock perfect pass the test. The target board is ZRTECH EP2C5T144C8 CORE2-5U core board and PERI1-8KD supporting daughter card.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

clock_test/clk_1Hz.v
clock_test/clk_1Hz.v.bak
clock_test/clk_1Hz.qpf
clock_test/clk_1Hz.qsf
clock_test/clk_1Hz.map.summary
clock_test/clk_1Hz.flow.rpt
clock_test/clk_1Hz.tan.rpt
clock_test/clk_1Hz.pin
clock_test/clk_1Hz.fit.smsg
clock_test/clk_1Hz.fit.summary
clock_test/clk_1Hz.cdf
clock_test/clk_1Hz.map.rpt
clock_test/shift8.v
clock_test/clk_1Hz.sof
clock_test/clk_1Hz.pof
clock_test/clk_1Hz.fit.rpt
clock_test/clk_1Hz.asm.rpt
clock_test/clk_1Hz.tan.summary
clock_test/shift8.v.bak
clock_test/sec.v
clock_test/sec.v.bak
clock_test/sec.bsf
clock_test/clk_1Hz.done
clock_test/clk_1Hz.bsf
clock_test/clk_1Hz.dpf
clock_test/min.v
clock_test/min.bsf
clock_test/shift8.bsf
clock_test/hour.v
clock_test/CORE2-5U-SLOT1.tcl
clock_test/min.v.bak
clock_test/hour.bsf
clock_test/seltimev.v
clock_test/SELTIMEV.bsf
clock_test/decodev.v
clock_test/SELTIMEv_zh.v
clock_test/DECODEV.bsf
clock_test/SELTIMEv_zh.v.bak
clock_test/decodev.v.bak
clock_test/clk_half.v
clock_test/clk_half.bsf
clock_test/简易数字钟BDF文件.pdf
clock_test/hour.v.bak
clock_test/clk_1Hz.qws
clock_test/Block1.bdf
clock_test/clk_1Hz.map.smsg
clock_test/incremental_db/README
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.cmp.dfp
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.map.kpt
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.cmp.rcfdb
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.cmp.cdb
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.cmp.hdb
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.map.dpi
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.cmp.re.rcfdb
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.cmp.logdb
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.cmp.kpt
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.map.cdb
clock_test/incremental_db/compiled_partitions/clk_1Hz.root_partition.map.hdb
clock_test/db/prev_cmp_clk_1Hz.qmsg
clock_test/db/clk_1Hz.db_info
clock_test/db/clk_1Hz.map.qmsg
clock_test/db/prev_cmp_clk_1Hz.map.qmsg
clock_test/db/clk_1Hz.cmp.cdb
clock_test/db/prev_cmp_clk_1Hz.fit.qmsg
clock_test/db/prev_cmp_clk_1Hz.asm.qmsg
clock_test/db/logic_util_heursitic.dat
clock_test/db/prev_cmp_clk_1Hz.tan.qmsg
clock_test/db/clk_1Hz.cbx.xml
clock_test/db/clk_1Hz.hif
clock_test/db/clk_1Hz.(0).cnf.cdb
clock_test/db/clk_1Hz.(0).cnf.hdb
clock_test/db/clk_1Hz.hier_info
clock_test/db/clk_1Hz.rtlv_sg_swap.cdb
clock_test/db/clk_1Hz.smart_action.txt
clock_test/db/clk_1Hz.lpc.txt
clock_test/db/clk_1Hz.tis_db_list.ddb
clock_test/db/clk_1Hz.lpc.html
clock_test/db/clk_1Hz.fit.qmsg
clock_test/db/clk_1Hz.cmp.logdb
clock_test/db/clk_1Hz.asm.qmsg
clock_test/db/clk_1Hz.pre_map.cdb
clock_test/db/clk_1Hz.tan.qmsg
clock_test/db/clk_1Hz.(1).cnf.cdb
clock_test/db/clk_1Hz.(1).cnf.hdb
clock_test/db/clk_1Hz.pre_map.hdb
clock_test/db/clk_1Hz.syn_hier_info
clock_test/db/clk_1Hz.(2).cnf.cdb
clock_test/db/clk_1Hz.(5).cnf.cdb
clock_test/db/clk_1Hz.(5).cnf.hdb
clock_test/db/clk_1Hz.(6).cnf.cdb
clock_test/db/clk_1Hz.(6).cnf.hdb
clock_test/db/clk_1Hz.map.ecobp
clock_test/db/clk_1Hz.map.kpt
clock_test/db/clk_1Hz.cmp_merge.kpt
clock_test/db/clk_1Hz.(2).cnf.hdb
clock_test/db/clk_1Hz.(8).cnf.cdb
clock_test/db/clk_1Hz.(7).cnf.cdb
clock_test/db/clk_1Hz.(3).cnf.cdb
clock_test/db/clk_1Hz.(7).cnf.hdb
clock_test/db/clk_1Hz.(3).cnf.hdb
clock_test/db/clk_1Hz.cmp2.ddb
clock_test/db/clk_1Hz.(4).cnf.cdb
clock_test/db/clk_1Hz.map_bb.logdb
clock_test/db/clk_1Hz.sld_design_entry.sci
clock_test/db/clk_1Hz.sgdiff.cdb
clock_test/db/clk_1Hz.cmp.kpt
clock_test/db/clk_1Hz.(4).cnf.hdb
clock_test/db/clk_1Hz.cmp.ecobp
clock_test/db/clk_1Hz.rtlv_sg.cdb
clock_test/db/clk_1Hz.(8).cnf.hdb
clock_test/db/clk_1Hz.lpc.rdb
clock_test/db/clk_1Hz.rtlv.hdb
clock_test/db/clk_1Hz.sgdiff.hdb
clock_test/db/clk_1Hz.sld_design_entry_dsc.sci
clock_test/db/clk_1Hz.cmp.bpm
clock_test/db/clk_1Hz.map_bb.cdb
clock_test/db/clk_1Hz.map.cdb
clock_test/db/clk_1Hz.map_bb.hdb
clock_test/db/clk_1Hz.map.hdb
clock_test/db/clk_1Hz.map.logdb
clock_test/db/clk_1Hz.map.bpm
clock_test/db/clk_1Hz.cmp.tdb
clock_test/db/clk_1Hz.cmp.hdb
clock_test/db/clk_1Hz.asm.rdb
clock_test/db/clk_1Hz.asm_labs.ddb
clock_test/db/clk_1Hz.eco.cdb
clock_test/db/clk_1Hz.cmp.rdb
clock_test/db/clk_1Hz.cmp0.ddb
clock_test/incremental_db/compiled_partitions
clock_test/incremental_db
clock_test/db
clock_test

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