文件名称:interp_24_cic
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基于fpga的插值CIC滤波器设计,采用verilog编写,24倍插值,仿真通过-Fpga-based interpolation CIC filter design using verilog write, 24x interpolation, through simulation
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下载文件列表
interp_24_cic/scr/cic_interp24.v
interp_24_cic/scr/cic_interp_arithmetic.v
interp_24_cic/scr/derivative_filter.v
interp_24_cic/scr/monopole_integrator_first.v
interp_24_cic/scr/multilevel_der_filter.v
interp_24_cic/scr/multilevel_integrator.v
interp_24_cic/scr/signal_gen0.v
interp_24_cic/scr/tb_cic.v
interp_24_cic/sim/out_data.dat
interp_24_cic/sim/signal_1m.dat
interp_24_cic/sim/signal_1m.dat.bak
interp_24_cic/sim/signal_data.dat
interp_24_cic/sim/vsim.wlf
interp_24_cic/sim/wave.do
interp_24_cic/sim/work/cic_interp24/verilog.asm
interp_24_cic/sim/work/cic_interp24/verilog.rw
interp_24_cic/sim/work/cic_interp24/_primary.dat
interp_24_cic/sim/work/cic_interp24/_primary.dbs
interp_24_cic/sim/work/cic_interp24/_primary.vhd
interp_24_cic/sim/work/cic_interp_arithmetic/verilog.asm
interp_24_cic/sim/work/cic_interp_arithmetic/verilog.rw
interp_24_cic/sim/work/cic_interp_arithmetic/_primary.dat
interp_24_cic/sim/work/cic_interp_arithmetic/_primary.dbs
interp_24_cic/sim/work/cic_interp_arithmetic/_primary.vhd
interp_24_cic/sim/work/derivative_filter/verilog.asm
interp_24_cic/sim/work/derivative_filter/verilog.rw
interp_24_cic/sim/work/derivative_filter/_primary.dat
interp_24_cic/sim/work/derivative_filter/_primary.dbs
interp_24_cic/sim/work/derivative_filter/_primary.vhd
interp_24_cic/sim/work/monopole_integrator_first/verilog.asm
interp_24_cic/sim/work/monopole_integrator_first/verilog.rw
interp_24_cic/sim/work/monopole_integrator_first/_primary.dat
interp_24_cic/sim/work/monopole_integrator_first/_primary.dbs
interp_24_cic/sim/work/monopole_integrator_first/_primary.vhd
interp_24_cic/sim/work/multilevel_der_filter/verilog.asm
interp_24_cic/sim/work/multilevel_der_filter/verilog.rw
interp_24_cic/sim/work/multilevel_der_filter/_primary.dat
interp_24_cic/sim/work/multilevel_der_filter/_primary.dbs
interp_24_cic/sim/work/multilevel_der_filter/_primary.vhd
interp_24_cic/sim/work/multilevel_integrator/verilog.asm
interp_24_cic/sim/work/multilevel_integrator/verilog.rw
interp_24_cic/sim/work/multilevel_integrator/_primary.dat
interp_24_cic/sim/work/multilevel_integrator/_primary.dbs
interp_24_cic/sim/work/multilevel_integrator/_primary.vhd
interp_24_cic/sim/work/signal_gen0/verilog.asm
interp_24_cic/sim/work/signal_gen0/verilog.rw
interp_24_cic/sim/work/signal_gen0/_primary.dat
interp_24_cic/sim/work/signal_gen0/_primary.dbs
interp_24_cic/sim/work/signal_gen0/_primary.vhd
interp_24_cic/sim/work/tb_cic/verilog.asm
interp_24_cic/sim/work/tb_cic/verilog.rw
interp_24_cic/sim/work/tb_cic/_primary.dat
interp_24_cic/sim/work/tb_cic/_primary.dbs
interp_24_cic/sim/work/tb_cic/_primary.vhd
interp_24_cic/sim/work/_info
interp_24_cic/sim/work/_temp/vlog2swkcn
interp_24_cic/sim/work/_temp/vlog66ni5c
interp_24_cic/sim/work/_temp/vlog9metaz
interp_24_cic/sim/work/_temp/vlog9yet7z
interp_24_cic/sim/work/_temp/vlogc1gef8
interp_24_cic/sim/work/_temp/vlogc77ww9
interp_24_cic/sim/work/_temp/vlogcm6w2a
interp_24_cic/sim/work/_temp/vlogcwge68
interp_24_cic/sim/work/_temp/vloge7tr4a
interp_24_cic/sim/work/_temp/vlogeysr7a
interp_24_cic/sim/work/_temp/vlogg0bdjs
interp_24_cic/sim/work/_temp/vlogg9bdgs
interp_24_cic/sim/work/_temp/vloghg9g46
interp_24_cic/sim/work/_temp/vloghs9g16
interp_24_cic/sim/work/_temp/vlogwandw3
interp_24_cic/sim/work/_temp/vlogx7a115
interp_24_cic/sim/work/_temp/vlogxga1y4
interp_24_cic/sim/work/_temp/vlogxrdbd3
interp_24_cic/sim/work/_vmake
interp_24_cic/sim/work.cr.mti
interp_24_cic/sim/work.mpf
interp_24_cic/sin_gen.m
interp_24_cic/~$波器操作说明.doc
interp_24_cic/~WRL0001.tmp
interp_24_cic/滤波器操作说明.doc
interp_24_cic/资料/CIC滤波器的优化设计及FPGA实现.pdf
interp_24_cic/资料/基于FPGA实现高插入CIC滤波器.pdf
interp_24_cic/资料/多速率采样中的CIC滤波器设计与分析.pdf
interp_24_cic/资料/测试文件_多速率信号处理[1].pdf
interp_24_cic/资料/第5章_信号的抽取与插值.pdf
interp_24_cic/资料/第八章__信号的抽取与插值.pdf
interp_24_cic/sim/work/cic_interp24
interp_24_cic/sim/work/cic_interp_arithmetic
interp_24_cic/sim/work/derivative_filter
interp_24_cic/sim/work/monopole_integrator_first
interp_24_cic/sim/work/multilevel_der_filter
interp_24_cic/sim/work/multilevel_integrator
interp_24_cic/sim/work/signal_gen0
interp_24_cic/sim/work/tb_cic
interp_24_cic/sim/work/_temp
interp_24_cic/sim/work
interp_24_cic/scr
interp_24_cic/sim
interp_24_cic/资料
interp_24_cic
interp_24_cic/scr/cic_interp_arithmetic.v
interp_24_cic/scr/derivative_filter.v
interp_24_cic/scr/monopole_integrator_first.v
interp_24_cic/scr/multilevel_der_filter.v
interp_24_cic/scr/multilevel_integrator.v
interp_24_cic/scr/signal_gen0.v
interp_24_cic/scr/tb_cic.v
interp_24_cic/sim/out_data.dat
interp_24_cic/sim/signal_1m.dat
interp_24_cic/sim/signal_1m.dat.bak
interp_24_cic/sim/signal_data.dat
interp_24_cic/sim/vsim.wlf
interp_24_cic/sim/wave.do
interp_24_cic/sim/work/cic_interp24/verilog.asm
interp_24_cic/sim/work/cic_interp24/verilog.rw
interp_24_cic/sim/work/cic_interp24/_primary.dat
interp_24_cic/sim/work/cic_interp24/_primary.dbs
interp_24_cic/sim/work/cic_interp24/_primary.vhd
interp_24_cic/sim/work/cic_interp_arithmetic/verilog.asm
interp_24_cic/sim/work/cic_interp_arithmetic/verilog.rw
interp_24_cic/sim/work/cic_interp_arithmetic/_primary.dat
interp_24_cic/sim/work/cic_interp_arithmetic/_primary.dbs
interp_24_cic/sim/work/cic_interp_arithmetic/_primary.vhd
interp_24_cic/sim/work/derivative_filter/verilog.asm
interp_24_cic/sim/work/derivative_filter/verilog.rw
interp_24_cic/sim/work/derivative_filter/_primary.dat
interp_24_cic/sim/work/derivative_filter/_primary.dbs
interp_24_cic/sim/work/derivative_filter/_primary.vhd
interp_24_cic/sim/work/monopole_integrator_first/verilog.asm
interp_24_cic/sim/work/monopole_integrator_first/verilog.rw
interp_24_cic/sim/work/monopole_integrator_first/_primary.dat
interp_24_cic/sim/work/monopole_integrator_first/_primary.dbs
interp_24_cic/sim/work/monopole_integrator_first/_primary.vhd
interp_24_cic/sim/work/multilevel_der_filter/verilog.asm
interp_24_cic/sim/work/multilevel_der_filter/verilog.rw
interp_24_cic/sim/work/multilevel_der_filter/_primary.dat
interp_24_cic/sim/work/multilevel_der_filter/_primary.dbs
interp_24_cic/sim/work/multilevel_der_filter/_primary.vhd
interp_24_cic/sim/work/multilevel_integrator/verilog.asm
interp_24_cic/sim/work/multilevel_integrator/verilog.rw
interp_24_cic/sim/work/multilevel_integrator/_primary.dat
interp_24_cic/sim/work/multilevel_integrator/_primary.dbs
interp_24_cic/sim/work/multilevel_integrator/_primary.vhd
interp_24_cic/sim/work/signal_gen0/verilog.asm
interp_24_cic/sim/work/signal_gen0/verilog.rw
interp_24_cic/sim/work/signal_gen0/_primary.dat
interp_24_cic/sim/work/signal_gen0/_primary.dbs
interp_24_cic/sim/work/signal_gen0/_primary.vhd
interp_24_cic/sim/work/tb_cic/verilog.asm
interp_24_cic/sim/work/tb_cic/verilog.rw
interp_24_cic/sim/work/tb_cic/_primary.dat
interp_24_cic/sim/work/tb_cic/_primary.dbs
interp_24_cic/sim/work/tb_cic/_primary.vhd
interp_24_cic/sim/work/_info
interp_24_cic/sim/work/_temp/vlog2swkcn
interp_24_cic/sim/work/_temp/vlog66ni5c
interp_24_cic/sim/work/_temp/vlog9metaz
interp_24_cic/sim/work/_temp/vlog9yet7z
interp_24_cic/sim/work/_temp/vlogc1gef8
interp_24_cic/sim/work/_temp/vlogc77ww9
interp_24_cic/sim/work/_temp/vlogcm6w2a
interp_24_cic/sim/work/_temp/vlogcwge68
interp_24_cic/sim/work/_temp/vloge7tr4a
interp_24_cic/sim/work/_temp/vlogeysr7a
interp_24_cic/sim/work/_temp/vlogg0bdjs
interp_24_cic/sim/work/_temp/vlogg9bdgs
interp_24_cic/sim/work/_temp/vloghg9g46
interp_24_cic/sim/work/_temp/vloghs9g16
interp_24_cic/sim/work/_temp/vlogwandw3
interp_24_cic/sim/work/_temp/vlogx7a115
interp_24_cic/sim/work/_temp/vlogxga1y4
interp_24_cic/sim/work/_temp/vlogxrdbd3
interp_24_cic/sim/work/_vmake
interp_24_cic/sim/work.cr.mti
interp_24_cic/sim/work.mpf
interp_24_cic/sin_gen.m
interp_24_cic/~$波器操作说明.doc
interp_24_cic/~WRL0001.tmp
interp_24_cic/滤波器操作说明.doc
interp_24_cic/资料/CIC滤波器的优化设计及FPGA实现.pdf
interp_24_cic/资料/基于FPGA实现高插入CIC滤波器.pdf
interp_24_cic/资料/多速率采样中的CIC滤波器设计与分析.pdf
interp_24_cic/资料/测试文件_多速率信号处理[1].pdf
interp_24_cic/资料/第5章_信号的抽取与插值.pdf
interp_24_cic/资料/第八章__信号的抽取与插值.pdf
interp_24_cic/sim/work/cic_interp24
interp_24_cic/sim/work/cic_interp_arithmetic
interp_24_cic/sim/work/derivative_filter
interp_24_cic/sim/work/monopole_integrator_first
interp_24_cic/sim/work/multilevel_der_filter
interp_24_cic/sim/work/multilevel_integrator
interp_24_cic/sim/work/signal_gen0
interp_24_cic/sim/work/tb_cic
interp_24_cic/sim/work/_temp
interp_24_cic/sim/work
interp_24_cic/scr
interp_24_cic/sim
interp_24_cic/资料
interp_24_cic
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