compu1/RISC_SPM_vhdl.prj
compu1/isim.log
compu1/compu.ntrc_log
compu1/Control_Unit.v
compu1/RISC_SPM.ngr
compu1/RISC_SPM.ngc
compu1/RISC_SPM.stx
compu1/compu.ise_ISE_Backup
compu1/RISC_SPM.bld
compu1/RISC_SPM.ngd
compu1/RISC_SPM_prev_built.ngd
compu1/RISC_SPM_map.mrp
compu1/RISC_SPM_map.ngm
compu1/RISC_SPM.v
compu1/RISC_SPM_summary.html
compu1/Processing_Unit.v
compu1/Memory_Unit.vhd
compu1/Memory_Unit.v
compu1/Register_Unit.v
compu1/D_flop.v
compu1/Address_Register.v
compu1/Instruction_Register.v
compu1/Program_Counter.v
compu1/Multiplexer_5ch.v
compu1/Multiplexer_3ch.v
compu1/Alu_RISC.v
compu1/RISC_SPM.prj
compu1/RISC_SPM.xst
compu1/RISC_SPM.cmd_log
compu1/RISC_SPM.syr
compu1/RISC_SPM.lso
compu1/isimwavedata.xwv
compu1/isim.hdlsourcefiles
compu1/compu.ise
compu1/.lso
compu1/RISC_SPM_map.ncd
compu1/RISC_SPM_usage.xml
compu1/RISC_SPM.par
compu1/RISC_SPM.ncd
compu1/RISC_SPM.xpi
compu1/RISC_SPM_pad.csv
compu1/RISC_SPM.pad
compu1/RISC_SPM_pad.txt
compu1/RISC_SPM.unroutes
compu1/risc_spm.twx
compu1/risc_spm.twr
compu1/risc_spm.bgn
compu1/risc_spm.drc
compu1/risc_spm.bit
compu1/_impact.log
compu1/_impact.cmd
compu1/xilinxsim.ini
compu1/testbench_isim_beh.exe
compu1/testbench.v
compu1/testbench_v_beh.prj
compu1/isim.cmd
compu1/testbench_v_isim_beh.exe
compu1/RISC_SPM.ucf
compu1/RISC_SPM.lfp
compu1/RISC_SPM.pcf
compu1/RISC_SPM.ut
compu1/device_usage_statistics.html
compu1/RISC_SPM.cel
compu1/test_RISC_SPM.v
compu1/testbench_beh.prj
compu1/RISC_SPM_last_par.ncd
compu1/isim.tmp_save/_1
compu1/isim.tmp_save
compu1/isim/work/hdllib.ref
compu1/isim/work/hdpdeps.ref
compu1/isim/work/vlg6C/testbench.bin
compu1/isim/work/vlg6C
compu1/isim/work/testbench/testbench.h
compu1/isim/work/testbench/xsimtestbench.cpp
compu1/isim/work/testbench/mingw/testbench.obj
compu1/isim/work/testbench/mingw
compu1/isim/work/testbench
compu1/isim/work/glbl/glbl.h
compu1/isim/work/glbl/mingw/glbl.obj
compu1/isim/work/glbl/mingw
compu1/isim/work/glbl
compu1/isim/work/vlg2D/glbl.bin
compu1/isim/work/vlg2D
compu1/isim/work/testbench__v/testbench__v.h
compu1/isim/work/testbench__v/xsimtestbench__v.cpp
compu1/isim/work/testbench__v/mingw/testbench__v.obj
compu1/isim/work/testbench__v/mingw
compu1/isim/work/testbench__v
compu1/isim/work/vlg5D/testbench__v.bin
compu1/isim/work/vlg5D
compu1/isim/work/_r_i_s_c___s_p_m/_r_i_s_c___s_p_m.h
compu1/isim/work/_r_i_s_c___s_p_m/mingw/_r_i_s_c___s_p_m.obj
compu1/isim/work/_r_i_s_c___s_p_m/mingw
compu1/isim/work/_r_i_s_c___s_p_m
compu1/isim/work/vlg18/_r_i_s_c___s_p_m.bin
compu1/isim/work/vlg18
compu1/isim/work/_control___unit/_control___unit.h
compu1/isim/work/_control___unit/mingw/_control___unit.obj
compu1/isim/work/_control___unit/mingw
compu1/isim/work/_control___unit
compu1/isim/work/_memory___unit/_memory___unit.h
compu1/isim/work/_memory___unit/xsim_memory___unit.cpp
compu1/isim/work/_memory___unit/mingw/_memory___unit.obj
compu1/isim/work/_memory___unit/mingw
compu1/isim/work/_memory___unit
compu1/isim/work/vlg4C/_memory___unit.bin
compu1/isim/work/vlg4C
compu1/isim/work/_processing___unit/_processing___unit.h
compu1/isim/work/_processing___unit/mingw/_processing___unit.obj
compu1/isim/work/_processing___unit/mingw
compu1/isim/work/_processing___unit
compu1/isim/work/vlg44/_processing___unit.bin
compu1/isim/work/vlg44
compu1/isim/work/_address___register/_address___register.h
compu1/isim/work/_address___register/mingw/_address___register.obj
compu1/isim/work/_address___register/mingw
compu1/isim/work/_address___register
compu1/isim/work/vlg0A/_address___register.bin
compu1/isim/work/vlg0A
compu1/isim/work/_alu___r_i_s_c/_alu___r_i_s_c.h
compu1/isim/work/_alu___r_i_s_c/mingw/_alu___r_i_s_c.obj
compu1/isim/work/_alu___r_i_s_c/mingw
compu1/isim/work/_alu___r_i_s_c
compu1/isim/work/vlg6E/_alu___r_i_s_c.bin
compu1/isim/work/vlg6E
compu1/isim/work/_d__flop/_d__flop.h
compu1/isim/work/_d__flop/mingw/_d__flop.obj
compu1/isim/work/_d__flop/mingw
compu1/isim/work/_d__flop
compu1/isim/work/vlg78/_d__flop.bin
compu1/isim/work/vlg78
compu1/isim/work/_instruction___register/_instruction___register.h
compu1/isim/work/_instruction___register/mingw/_instruction___register.obj
compu1/isim/work/_instruction___register/mingw
compu1/isim/work/_instruction___register
compu1/isim/work/vlg3A/_instruction___register.bin
compu1/isim/work/vlg3A
compu1/isim/work/_multiplexer__3ch/_multiplexer__3ch.h
compu1/isim/work/_multiplexer__3ch/mingw/_multiplexer__3ch.obj
compu1/isim/work/_multiplexer__3ch/mingw
compu1/isim/work/_multiplexer__3ch
compu1/isim/work/vlg24/_multiplexer__3ch.bin
compu1/isim/work/vlg24/_control___unit.bin
compu1/isim/work/vlg24
compu1/isim/work/_multiplexer__5ch/_multiplexer__5ch.h
compu1/isim/work/_multiplexer__5ch/mingw/_multiplexer__5ch.obj
compu1/isim/work/_multiplexer__5ch/mingw
compu1/isim/work/_multiplexer__5ch
compu1/isim/work/vlg56/_multiplexer__5ch.bin
compu1/isim/work/vlg56
compu1/isim/work/_program___counter/_program___counter.h
compu1/isim/work/_program___counter/mingw/_program___counter.obj
compu1/isim/work/_program___counter/mingw
compu1/isim/work/_program___counter
compu1/isim/work/vlg4B/_program___counter.bin
compu