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文件名称:ZedBoard_OOB_Design

  • 所属分类：
    Linux-Unix program
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-05-31
  • 文件大小：
    7.73mb
  • 已下载：
    0次
  • 提 供 者：
    y*****
  • 相关连接：
    无
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linux（8M）在zedboard上运行的所有必要文件。-necessary documents for linux (8M) running on the zedboard
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/text-base/user_logic.v.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/text-base/cf_clkgen.v.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/prop-base/user_logic.v.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/prop-base/cf_clkgen.v.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/vhdl/.svn/text-base/axi_clkgen.vhd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/vhdl/.svn/prop-base/axi_clkgen.vhd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/.svn/text-base/tx_package.vhd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/.svn/text-base/tx_encoder.vhd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/.svn/text-base/axi_spdif_tx.vhd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/.svn/text-base/tx_bitbuf.vhd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/.svn/text-base/user_logic.vhd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/entries
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/vhdl/.svn/entries
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/_axi_clkgen_xst.prj.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/axi_clkgen_v2_1_0.pao.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/axi_clkgen_v2_1_0.mpd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/_axi_clkgen_xst.prj.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/axi_clkgen_v2_1_0.pao.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/axi_clkgen_v2_1_0.mpd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/.svn/entries
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/data/.svn/text-base/_axi_spdif_tx_xst.prj.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/data/.svn/text-base/axi_spdif_tx_v2_1_0.pao.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/data/.svn/text-base/axi_spdif_tx_v2_1_0.mpd.svn-base
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/user_logic.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/cf_clkgen.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/vhdl/axi_clkgen.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/entries
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/tx_package.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/tx_bitbuf.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/tx_encoder.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/user_logic.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/axi_spdif_tx.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/data/.svn/entries
ZedBoard_OOB_Design/hw/xps_proj/pcores/vga_flyinglogo_v1_00_a/hdl/vhdl/vga_flyinglogo.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/vga_flyinglogo_v1_00_a/hdl/vhdl/video_merge.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/vga_flyinglogo_v1_00_a/hdl/vhdl/sync_gen.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/vga_flyinglogo_v1_00_a/hdl/vhdl/logo_bram.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_add.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_csc_1.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_csc_RGB2CrYCb.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_hdmi.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_hdmi_tx_16b.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_mem.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_mul.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_ss_444to422.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_vdma.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/user_logic.v
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/vhdl/axi_hdmi_tx_16b.vhd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/axi_clkgen_v2_1_0.pao
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/axi_clkgen_v2_1_0.mpd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/_axi_clkgen_xst.prj
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/data/axi_spdif_tx_v2_1_0.pao
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/data/axi_spdif_tx_v2_1_0.mpd
ZedBoard_OOB_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/data/_axi_spdif_tx_xst.prj
ZedBoard_OOB_Design/hw/xps_proj/pcores/vga_flyinglogo_v1_

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