文件名称:VHDL_book1
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gate:基本逻辑门的实现和验证
mux4_1_gate:多路复用器的门级实现和验证
mux4_1_behav:多路复用器的行为级实现和验证
seg7_gate:7段数码管逻辑门实现和验证
seg7_behav:7段数码管case语句描述和验证
mux7seg:采用按键复用7段数码管的实现和验证
clkseg7:采用时钟自动扫描复用7段数码管的实现和验证
comp4_gate:4位比较器结构化实现和验证
comp8_behav:8位比较器行为实现和验证
decode3_8_gate:3-8译码器的逻辑门实现和验证
decode3_8_behav:3-8译码器的case语句实现和验证
encode8_3_gate:8-3编码器的门级实现和验证
encode8_3_behav:8-3编码器的逻辑门实现和验证
priority_encoder8_3: 8-3优先级编码器的循环语句实现和验证
binbcd4_gate:4位二进制码到BCD码变换设计
binbcd8_behav:8位二进制码到BCD码变换设计
bin_gray4_gate:4位二进制码到Gray码的变换设计
binbcd4_gate:4位Gray码到二进制码变换设计-gate: the realization of basic logic gates and verification mux4_1_gate: multiplexer gate-level implementation and verification mux4_1_behav: Multiplexer behavioral implementation and verification seg7_gate: 7-segment digital tube logic gate implementation and verification seg7_behav: 7 segment digital tube case statements describe and validate mux7seg: using buttons multiplex seven segment LED implementation and verification clkseg7: clock automatically scans using 7-segment digital tube multiplex implementation and verification comp4_gate: 4-bit comparator structured implementation and verification comp8_behav: 8-bit comparator behavior implementation and verification decode3_8_gate :3-8 decoder logic gate implementation and verification decode3_8_behav :3-8 decoder implementation and verification of case statement encode8_3_gate :8-3 encoder gate-level implementation and verification encode8_3_behav :8-3 encoder implementation and verification of logic gates priority_encoder8_3: 8-3
mux4_1_gate:多路复用器的门级实现和验证
mux4_1_behav:多路复用器的行为级实现和验证
seg7_gate:7段数码管逻辑门实现和验证
seg7_behav:7段数码管case语句描述和验证
mux7seg:采用按键复用7段数码管的实现和验证
clkseg7:采用时钟自动扫描复用7段数码管的实现和验证
comp4_gate:4位比较器结构化实现和验证
comp8_behav:8位比较器行为实现和验证
decode3_8_gate:3-8译码器的逻辑门实现和验证
decode3_8_behav:3-8译码器的case语句实现和验证
encode8_3_gate:8-3编码器的门级实现和验证
encode8_3_behav:8-3编码器的逻辑门实现和验证
priority_encoder8_3: 8-3优先级编码器的循环语句实现和验证
binbcd4_gate:4位二进制码到BCD码变换设计
binbcd8_behav:8位二进制码到BCD码变换设计
bin_gray4_gate:4位二进制码到Gray码的变换设计
binbcd4_gate:4位Gray码到二进制码变换设计-gate: the realization of basic logic gates and verification mux4_1_gate: multiplexer gate-level implementation and verification mux4_1_behav: Multiplexer behavioral implementation and verification seg7_gate: 7-segment digital tube logic gate implementation and verification seg7_behav: 7 segment digital tube case statements describe and validate mux7seg: using buttons multiplex seven segment LED implementation and verification clkseg7: clock automatically scans using 7-segment digital tube multiplex implementation and verification comp4_gate: 4-bit comparator structured implementation and verification comp8_behav: 8-bit comparator behavior implementation and verification decode3_8_gate :3-8 decoder logic gate implementation and verification decode3_8_behav :3-8 decoder implementation and verification of case statement encode8_3_gate :8-3 encoder gate-level implementation and verification encode8_3_behav :8-3 encoder implementation and verification of logic gates priority_encoder8_3: 8-3
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下载文件列表
VHDL_book1/
VHDL_book1/binbcd4_gate/
VHDL_book1/binbcd4_gate/binbcd4.vhd
VHDL_book1/binbcd4_gate/binbcd4_gate.ise
VHDL_book1/binbcd4_gate/binbcd4_gate.ntrc_log
VHDL_book1/binbcd4_gate/binbcd4_gate.restore
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise.lock
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/version
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/Autonym/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/common/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/ISimPlugin/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/ISimPlugin/SignalOrdering1/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/ISimPlugin/SignalOrdering1/test_isim_beh.exe
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/ISimPlugin/SignalOrdering1/test_isim_beh.exe_StrTbl
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
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VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/
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VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module
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VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/Autonym/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/bitgen/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/common/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/common/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/cpldfit/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/dumpngdio/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/fuse/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/Hierarchi
VHDL_book1/binbcd4_gate/
VHDL_book1/binbcd4_gate/binbcd4.vhd
VHDL_book1/binbcd4_gate/binbcd4_gate.ise
VHDL_book1/binbcd4_gate/binbcd4_gate.ntrc_log
VHDL_book1/binbcd4_gate/binbcd4_gate.restore
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise.lock
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/version
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__OBJSTORE__/
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VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/bitgen/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/common/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/common/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/cpldfit/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/dumpngdio/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/fuse/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/
VHDL_book1/binbcd4_gate/binbcd4_gate_xdb/tmp/ise/__REGISTRY__/Hierarchi
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