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文件名称:ddc_v5

  • 所属分类：
    Other systems
  • 标签属性：
    [Matlab] [源码]
  • 上传时间：
    2013-06-11
  • 文件大小：
    648.71kb
  • 已下载：
    0次
  • 提 供 者：
    yuche******
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

wcdma数字下变频 是采用matlab 里面的simulink仿真工具和xilinx 的system generator 工作开发的，可以直接运行的，非常有参考价值-wcdma digital down conversion is used inside matlab simulink simulation tools and working to develop a xilinx system generator, and can run directly, very useful
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下载文件列表

ddc/Implementation/Sp3a/ddc_umts_sp3a_init.m
ddc/Implementation/Sp3a/ddc_umts_sp3a_post.m
ddc/Implementation/Sp3a/ddc_umts_sp3a_v1_0.mdl
ddc/Implementation/Sp3a/readme.txt
ddc/Implementation/VHDL/complex_mult_v5.vhd
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_h1.coe
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1.edn
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1.mif
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1.vhd
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1.vho
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1.xco
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1COEFF_auto0.mif
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1COEFF_auto_HALFBAND_CENTRE.mif
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1filt_decode_rom.mif
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1_fir_compiler_v3_0_xst_1.ngc
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1_flist.txt
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1_readme.txt
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1_unobf.ngc
ddc/Implementation/VHDL/cores/ddc_hf1/ddc_hf1_xmdf.tcl
ddc/Implementation/VHDL/cores/ddc_hf1/hex_ddc_hf1.mif
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_h2.coe
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2.edn
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2.mif
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2.vhd
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2.vho
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2.xco
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2COEFF_auto0.mif
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2COEFF_auto_HALFBAND_CENTRE.mif
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2filt_decode_rom.mif
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2_fir_compiler_v3_0_xst_1.ngc
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2_flist.txt
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2_readme.txt
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2_unobf.ngc
ddc/Implementation/VHDL/cores/ddc_hf2/ddc_hf2_xmdf.tcl
ddc/Implementation/VHDL/cores/ddc_hf2/hex_ddc_hf2.mif
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_h3.coe
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc.edn
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc.mif
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc.vhd
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc.vho
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc.xco
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrcCOEFF_auto0.mif
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrcCOEFF_auto1.mif
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrcfilt_decode_rom.mif
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc_fir_compiler_v3_0_xst_1.ngc
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc_flist.txt
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc_readme.txt
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc_unobf.ngc
ddc/Implementation/VHDL/cores/ddc_srrc/ddc_srrc_xmdf.tcl
ddc/Implementation/VHDL/cores/ddc_srrc/hex_ddc_srrc.mif
ddc/Implementation/VHDL/cores/dds/ddc_dds_v5.edn
ddc/Implementation/VHDL/cores/dds/ddc_dds_v5.vhd
ddc/Implementation/VHDL/cores/dds/ddc_dds_v5.vho
ddc/Implementation/VHDL/cores/dds/ddc_dds_v5.xco
ddc/Implementation/VHDL/cores/dds/ddc_dds_v5_dds_compiler_v1_1_xst_1.ngc
ddc/Implementation/VHDL/cores/dds/ddc_dds_v5_flist.txt
ddc/Implementation/VHDL/cores/dds/ddc_dds_v5_readme.txt
ddc/Implementation/VHDL/cores/dds/ddc_dds_v5_xmdf.tcl
ddc/Implementation/VHDL/cores/dsp48e/mac_v5.vhd
ddc/Implementation/VHDL/cores/dsp48e/mac_v5.xaw
ddc/Implementation/VHDL/cores/dsp48e/mac_v5_arwz.ucf
ddc/Implementation/VHDL/cores/mult/mult.edn
ddc/Implementation/VHDL/cores/mult/mult.vhd
ddc/Implementation/VHDL/cores/mult/mult.vho
ddc/Implementation/VHDL/cores/mult/mult.xco
ddc/Implementation/VHDL/cores/mult/mult_flist.txt
ddc/Implementation/VHDL/cores/mult/mult_mult_gen_v10_0_xst_1.ngc
ddc/Implementation/VHDL/cores/mult/mult_readme.txt
ddc/Implementation/VHDL/cores/mult/mult_xmdf.tcl
ddc/Implementation/VHDL/ddc_umts_bb_init.m
ddc/Implementation/VHDL/ddc_umts_post.m
ddc/Implementation/VHDL/ddc_umts_rtl_bb.mdl
ddc/Implementation/VHDL/ddc_umts_v5.vhd
ddc/Implementation/VHDL/ddc_umts_v5_bb_wrapper.vhd
ddc/Implementation/VHDL/ddc_umts_v5_bb_wrapper_config.m
ddc/Implementation/VHDL/freq_translate.vhd
ddc/Implementation/VHDL/mac_v5.vhd
ddc/Implementation/VHDL/mixer_v5.vhd
ddc/Implementation/VHDL/readme.txt
ddc/Implementation/Virtex5/ddc_umts_init.m
ddc/Implementation/Virtex5/ddc_umts_post.m
ddc/Implementation/Virtex5/ddc_umts_virtex5_v1_0.mdl
ddc/Implementation/Virtex5/readme.txt
ddc/Model/acs_test_input.p
ddc/Model/calculate_ddc_metrics.p
ddc/Model/conf1_h1.fda
ddc/Model/conf2_h1.fda
ddc/Model/conf2_h2.fda
ddc/Model/ddc_conf1_h1.m
ddc/Model/ddc_conf2_h1.m
ddc/Model/ddc_conf2_h2.m
ddc/Model/ddc_h1.coe
ddc/Model/ddc_h2.coe
ddc/Model/ddc_h3.coe
ddc/Model/ddc_performance_metrics.p
ddc/Model/ddc_srrc.fda
ddc/Model/ddc_srrc.m
ddc/Model/dynamic_range_test_input.p
ddc/Model/halfband1.m
ddc/Model/halfband2.m
ddc/Model/halfband3.m
ddc/Model/intermodulation_input.p
ddc/Model/plot_psd_umts_duc_mask.p
ddc/Model/srrc.m
ddc/Model/sum_sinusoids_test_input.p
ddc/Model/umts_ddc_filter_conf1.m
ddc/Model/umts_ddc_filter_conf2.m
ddc/Model/umts_ddc_fix_point_model.m
ddc/Model/umts_ddc_input.p
ddc/Model/umts_duc_filter_conf1.m
ddc/Model/wcdma_

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