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文件名称:u-c

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-06-14
  • 文件大小：
    3.92mb
  • 已下载：
    0次
  • 提 供 者：
    xue****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

通过控制机控制CH376 USB芯片达到从机模式通信的目的，采用了低级建模的思想-By controlling the motor control chip CH376 USB slave mode to achieve the purpose of communication, the idea of ​ ​ using a low-level modeling
(系统自动生成,下载前可以参看下载内容)

下载文件列表

u-c/add_clk.bsf
u-c/add_clk.v
u-c/db/logic_util_heursitic.dat
u-c/db/prev_cmp_uc.qmsg
u-c/db/uc.(0).cnf.cdb
u-c/db/uc.(0).cnf.hdb
u-c/db/uc.(1).cnf.cdb
u-c/db/uc.(1).cnf.hdb
u-c/db/uc.(2).cnf.cdb
u-c/db/uc.(2).cnf.hdb
u-c/db/uc.(3).cnf.cdb
u-c/db/uc.(3).cnf.hdb
u-c/db/uc.(4).cnf.cdb
u-c/db/uc.(4).cnf.hdb
u-c/db/uc.(5).cnf.cdb
u-c/db/uc.(5).cnf.hdb
u-c/db/uc.(6).cnf.cdb
u-c/db/uc.(6).cnf.hdb
u-c/db/uc.(7).cnf.cdb
u-c/db/uc.(7).cnf.hdb
u-c/db/uc.(8).cnf.cdb
u-c/db/uc.(8).cnf.hdb
u-c/db/uc.amm.cdb
u-c/db/uc.asm.qmsg
u-c/db/uc.asm.rdb
u-c/db/uc.asm_labs.ddb
u-c/db/uc.cbx.xml
u-c/db/uc.cmp.bpm
u-c/db/uc.cmp.cdb
u-c/db/uc.cmp.hdb
u-c/db/uc.cmp.kpt
u-c/db/uc.cmp.logdb
u-c/db/uc.cmp.rdb
u-c/db/uc.cmp_merge.kpt
u-c/db/uc.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
u-c/db/uc.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
u-c/db/uc.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
u-c/db/uc.db_info
u-c/db/uc.eda.qmsg
u-c/db/uc.fit.qmsg
u-c/db/uc.hier_info
u-c/db/uc.hif
u-c/db/uc.idb.cdb
u-c/db/uc.lpc.html
u-c/db/uc.lpc.rdb
u-c/db/uc.lpc.txt
u-c/db/uc.map.bpm
u-c/db/uc.map.cdb
u-c/db/uc.map.hdb
u-c/db/uc.map.kpt
u-c/db/uc.map.logdb
u-c/db/uc.map.qmsg
u-c/db/uc.map_bb.cdb
u-c/db/uc.map_bb.hdb
u-c/db/uc.map_bb.logdb
u-c/db/uc.pre_map.cdb
u-c/db/uc.pre_map.hdb
u-c/db/uc.rtlv.hdb
u-c/db/uc.rtlv_sg.cdb
u-c/db/uc.rtlv_sg_swap.cdb
u-c/db/uc.sgdiff.cdb
u-c/db/uc.sgdiff.hdb
u-c/db/uc.sld_design_entry.sci
u-c/db/uc.sld_design_entry_dsc.sci
u-c/db/uc.smart_action.txt
u-c/db/uc.smp_dump.txt
u-c/db/uc.sta.qmsg
u-c/db/uc.sta.rdb
u-c/db/uc.sta_cmp.8_slow_1200mv_85c.tdb
u-c/db/uc.syn_hier_info
u-c/db/uc.tiscmp.fastest_slow_1200mv_0c.ddb
u-c/db/uc.tiscmp.fastest_slow_1200mv_85c.ddb
u-c/db/uc.tiscmp.fast_1200mv_0c.ddb
u-c/db/uc.tiscmp.slow_1200mv_0c.ddb
u-c/db/uc.tiscmp.slow_1200mv_85c.ddb
u-c/db/uc.tis_db_list.ddb
u-c/Effect_Usb.v
u-c/Effect_Usb.v.bak
u-c/Effect_Usb1.bsf
u-c/Effect_Usb1.v
u-c/Effect_Usb1.v.bak
u-c/Effect_Usb2.bsf
u-c/Effect_Usb2.v
u-c/Effect_Usb2.v.bak
u-c/Flashing.bsf
u-c/Flashing.v
u-c/Flashing.v.bak
u-c/incremental_db/compiled_partitions/uc.db_info
u-c/incremental_db/compiled_partitions/uc.root_partition.cmp.cdb
u-c/incremental_db/compiled_partitions/uc.root_partition.cmp.dfp
u-c/incremental_db/compiled_partitions/uc.root_partition.cmp.hdb
u-c/incremental_db/compiled_partitions/uc.root_partition.cmp.kpt
u-c/incremental_db/compiled_partitions/uc.root_partition.cmp.logdb
u-c/incremental_db/compiled_partitions/uc.root_partition.cmp.rcfdb
u-c/incremental_db/compiled_partitions/uc.root_partition.map.cdb
u-c/incremental_db/compiled_partitions/uc.root_partition.map.dpi
u-c/incremental_db/compiled_partitions/uc.root_partition.map.hbdb.cdb
u-c/incremental_db/compiled_partitions/uc.root_partition.map.hbdb.hb_info
u-c/incremental_db/compiled_partitions/uc.root_partition.map.hbdb.hdb
u-c/incremental_db/compiled_partitions/uc.root_partition.map.hbdb.sig
u-c/incremental_db/compiled_partitions/uc.root_partition.map.hdb
u-c/incremental_db/compiled_partitions/uc.root_partition.map.kpt
u-c/incremental_db/README
u-c/Read_Usb.bsf
u-c/Read_Usb.v
u-c/Read_Usb.v.bak
u-c/simulation/modelsim/msim_transcript
u-c/simulation/modelsim/Read_Usb.vt
u-c/simulation/modelsim/Read_Usb.vt.bak
u-c/simulation/modelsim/rtl_work/@effect_@usb1/verilog.prw
u-c/simulation/modelsim/rtl_work/@effect_@usb1/verilog.psm
u-c/simulation/modelsim/rtl_work/@effect_@usb1/_primary.dat
u-c/simulation/modelsim/rtl_work/@effect_@usb1/_primary.dbs
u-c/simulation/modelsim/rtl_work/@effect_@usb1/_primary.vhd
u-c/simulation/modelsim/rtl_work/@effect_@usb2/verilog.prw
u-c/simulation/modelsim/rtl_work/@effect_@usb2/verilog.psm
u-c/simulation/modelsim/rtl_work/@effect_@usb2/_primary.dat
u-c/simulation/modelsim/rtl_work/@effect_@usb2/_primary.dbs
u-c/simulation/modelsim/rtl_work/@effect_@usb2/_primary.vhd
u-c/simulation/modelsim/rtl_work/@flashing/verilog.prw
u-c/simulation/modelsim/rtl_work/@flashing/verilog.psm
u-c/simulation/modelsim/rtl_work/@flashing/_primary.dat
u-c/simulation/modelsim/rtl_work/@flashing/_primary.dbs
u-c/simulation/modelsim/rtl_work/@flashing/_primary.vhd
u-c/simulation/modelsim/rtl_work/@read_@usb/verilog.prw
u-c/simulation/modelsim/rtl_work/@read_@usb/verilog.psm
u-c/simulation/modelsim/rtl_work/@read_@usb/_primary.dat
u-c/simulation/modelsim/rtl_work/@read_@usb/_primary.dbs
u-c/simulation/modelsim/rtl_work/@read_@usb/_primary.vhd
u-c/simulation/modelsim/rtl_work/@write_@usb/verilog.prw
u-c/simulation/modelsim/rtl_work/@write_@usb/verilog.psm
u-c/simulation/modelsim/rtl_work/@write_@usb/_primary.dat
u-c/simulation/modelsim/rtl_work/@write_@usb/_primary.dbs
u-c/simulation/modelsim/rtl_work/@write_@usb/_primary.vhd
u-c/simulation/modelsim/rtl_work/add_clk/verilog.prw
u-c/simulation/modelsim/rtl_work/add_clk/verilog.psm
u-c/simulation/modelsim/rtl_work/add_clk/_primary.dat
u-c/simulation/modelsim/rtl_work/add_clk/_primary.dbs
u-c/simulation/modelsim/rtl_work/add_clk/_primary.vhd
u-c/simulation/modelsim/rtl_work/uc/verilog.prw
u-c/simulation/modelsim/rtl_work/uc/verilog.psm
u-c/simulation/modelsim/rtl_work/uc/_primary.dat
u-c/simulation/modelsim/rtl_work/uc/_prima

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