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文件名称:VLSI-Project-Median-filer

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-06-27
  • 文件大小：
    14.11mb
  • 已下载：
    0次
  • 提 供 者：
    刘****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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FPGA和ASIC实现的图像中值滤波模块，各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the USTC VLSI design optimization final project. With the final version of the report and the presention.
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下载文件列表

VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/compare3.v
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/compare3.v.bak
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/altsyncram_kga1.tdf
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/altsyncram_pga1.tdf
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/cmpr_ugc.tdf
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/cntr_ksf.tdf
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/logic_util_heursitic.dat
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(0).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(0).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(1).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(1).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(10).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(10).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(11).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(11).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(12).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(12).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(2).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(2).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(3).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(3).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(4).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(4).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(5).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(5).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(6).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(6).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(7).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(7).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(8).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(8).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(9).cnf.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.(9).cnf.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.ace_cmp.bpm
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.ace_cmp.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.ace_cmp.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.ae.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.amm.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.asm.qmsg
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.asm.rdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.asm_labs.ddb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.atom.rvd
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.atom_map.rvd
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cbx.xml
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cmp.bpm
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cmp.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cmp.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cmp.kpt
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cmp.logdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cmp.rdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cmp_merge.kpt
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.db_info
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.eco.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.fit.qmsg
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.hier_info
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.hif
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.idb.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.lpc.html
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.lpc.rdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.lpc.txt
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.map.bpm
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.map.cdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.map.hdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.map.kpt
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.map.logdb
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filter.map.qmsg
VLSI_Project_刘克辉_母志强/code/median_filter_FPGA/db/median_filt

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