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文件名称:Verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2013-07-03
  • 文件大小：
    14.54mb
  • 已下载：
    0次
  • 提 供 者：
    Juan*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

verilog入门资料，里面有很多实例及源码-verilog introductory information, there are many examples and source code
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Verilog设计与验证/
Verilog设计与验证/Verilog设计与验证.pdf
Verilog设计与验证/光盘/
Verilog设计与验证/光盘/Example-2-1/
Verilog设计与验证/光盘/Example-2-1/HelloVlog.v
Verilog设计与验证/光盘/Example-3-1/
Verilog设计与验证/光盘/Example-3-1/FullAdd.v
Verilog设计与验证/光盘/Example-3-1/transcript
Verilog设计与验证/光盘/Example-3-2/
Verilog设计与验证/光盘/Example-3-2/FullAdd.v
Verilog设计与验证/光盘/Example-3-3/
Verilog设计与验证/光盘/Example-3-3/CRC10.v
Verilog设计与验证/光盘/Example-4-1/
Verilog设计与验证/光盘/Example-4-10/
Verilog设计与验证/光盘/Example-4-10/bibus/
Verilog设计与验证/光盘/Example-4-10/bibus/bibus.prd
Verilog设计与验证/光盘/Example-4-10/bibus/bibus.prj
Verilog设计与验证/光盘/Example-4-10/bibus/bibus.v
Verilog设计与验证/光盘/Example-4-10/bibus/decode.v
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.fse
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.srd
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.srm
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.srr
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.srs
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.sxr
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.tcl
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.tlg
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.vqm
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus.xrf
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus_cons.tcl
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/bibus_rm.tcl
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/rpt_bibus.areasrr
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/rpt_bibus_areasrr.htm
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/syntmp/
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/syntmp/bibus.msg
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/syntmp/bibus.plg
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/syntmp/bibus_cons_ui.tcl
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/verif/
Verilog设计与验证/光盘/Example-4-10/bibus/rev_1/verif/bibus.vif
Verilog设计与验证/光盘/Example-4-10/bibus/syntmp.msg
Verilog设计与验证/光盘/Example-4-10/complex_bibus/
Verilog设计与验证/光盘/Example-4-10/complex_bibus/complex_bibus.prd
Verilog设计与验证/光盘/Example-4-10/complex_bibus/complex_bibus.prj
Verilog设计与验证/光盘/Example-4-10/complex_bibus/complex_bibus.v
Verilog设计与验证/光盘/Example-4-10/complex_bibus/complex_bibus2.v
Verilog设计与验证/光盘/Example-4-10/complex_bibus/counter.v
Verilog设计与验证/光盘/Example-4-10/complex_bibus/decode.v
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/AutoConstraint_complex_bibus.sdc
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.fse
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.srd
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.srm
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.srr
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.srs
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.sxr
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.tcl
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.tlg
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.vqm
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus.xrf
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.fse
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.srd
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.srm
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.srr
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.srs
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.sxr
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.tcl
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.tlg
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.vqm
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2.xrf
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2_cons.tcl
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus2_rm.tcl
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus_cons.tcl
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/complex_bibus_rm.tcl
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/decode.srr
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/par_1/
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/rpt_complex_bibus.areasrr
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/rpt_complex_bibus_areasrr.htm
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/syntmp/
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus.msg
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus.plg
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus2.plg
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus2_cons_ui.tcl
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus_cons_ui.tcl
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/verif/
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/verif/complex_bibus.vif
Verilog设计与验证/光盘/Example-4-10/complex_bibus/rev_1/verif/complex_bibus2.vif
Verilog设计与验证/光盘/Example-4-10/complex_bibus/syntmp.msg
Verilog设计与验证/光盘/Example-4-10/source/
Verilog设计与验证/光盘/Example-4-10/source/bibus.v
Verilog设计与验证/光盘/Example-4-10/source/complex_bibus.v
Verilog设计与验证/光盘/Example-4-10/source/complex_bibus2.

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