文件名称:VectCPU_1s40_0_81_nov0208
介绍说明－－下载内容来自于网络，使用问题请自行百度
国外博士写向量处理机，是和NIOS处理器一起开发的，对这个的研究比较透彻，希望对大家有用-Most previous research into vector architectures has concentrated on supercomputing applications
and small enhancements to existing vector supercomputer implementations. This thesis expands the body of
vector research by examining designs appropriate for single-chip full-custom vector microprocessor implementations
targeting a much broader range of applications.
I present the design, implementation, and evaluation of T0 (Torrent-0): the first single-chip vector
microprocessor. T0 is a compact but highly parallel processor that can sustain over 24 operations per
cycle while issuing only a single 32-bit instruction per cycle. T0 demonstrates that vector architectures
are well suited to full-custom VLSI implementation and that they perform well on many multimedia and
human-machine interface tasks.
The remainder of the thesis contains proposals for future vector microprocessor designs. I show
that the most area-efficient vector register file designs have several banks with severa
and small enhancements to existing vector supercomputer implementations. This thesis expands the body of
vector research by examining designs appropriate for single-chip full-custom vector microprocessor implementations
targeting a much broader range of applications.
I present the design, implementation, and evaluation of T0 (Torrent-0): the first single-chip vector
microprocessor. T0 is a compact but highly parallel processor that can sustain over 24 operations per
cycle while issuing only a single 32-bit instruction per cycle. T0 demonstrates that vector architectures
are well suited to full-custom VLSI implementation and that they perform well on many multimedia and
human-machine interface tasks.
The remainder of the thesis contains proposals for future vector microprocessor designs. I show
that the most area-efficient vector register file designs have several banks with severa
(系统自动生成,下载前可以参看下载内容)
下载文件列表
reg_memory.mif
scalarcore.stp
VectCPU_sys.qip
VectCPU_sys.qpf
VectCPU_sys.qsf
VectCPU_sys.sdc
assembler/
assembler/README.txt
assembler/src/
assembler/src/binutils/
assembler/src/binutils/gas/
assembler/src/binutils/gas/config/
assembler/src/binutils/gas/config/tc-nios2.c
assembler/src/binutils/include/
assembler/src/binutils/include/opcode/
assembler/src/binutils/include/opcode/nios2.h
assembler/src/binutils/opcodes/
assembler/src/binutils/opcodes/nios2-opc.c
assembler/Test/
assembler/Test/test.asm
assembler/Test/vector_testsuite_results.log
assembler/Test/vector_testsuite_results2.log
assembler/Test/vector_testsuite_results3.log
assembler/Test/vector_testsuite_results4.log
assembler/Test/vector_testsuite_results5(final).log
assembler/Test/v_assembler_test.s
assembler/Test/v_assembler_test_extracomma.s
assembler/Test/v_assembler_test_wrongreg.s
README.txt
VectCPU_sys.sopc
ip/
ip/utiie_cpu/
ip/utiie_cpu/cb_generator.pl
ip/utiie_cpu/class.ptf
ip/utiie_cpu/hdl/
ip/utiie_cpu/hdl/Adder_w_Comparator.v
ip/utiie_cpu/hdl/ALU_Logic.v
ip/utiie_cpu/hdl/Branch_Logic.v
ip/utiie_cpu/hdl/Control_Registers.v
ip/utiie_cpu/hdl/Control_Unit.v
ip/utiie_cpu/hdl/Datapath.v
ip/utiie_cpu/hdl/Decoder_Logic.v
ip/utiie_cpu/hdl/Instruction_Fetch_Unit.v
ip/utiie_cpu/hdl/Instr_Register.v
ip/utiie_cpu/hdl/isa_def.v
ip/utiie_cpu/hdl/Logic_Unit.v
ip/utiie_cpu/hdl/Memory_Address_Align.v
ip/utiie_cpu/hdl/Memory_Byteenable.v
ip/utiie_cpu/hdl/Memory_Data_In_Align.v
ip/utiie_cpu/hdl/Memory_Data_Out_Align.v
ip/utiie_cpu/hdl/Next_PC_Shifter_Selection.v
ip/utiie_cpu/hdl/OpA_Selection.v
ip/utiie_cpu/hdl/OpB_Imm_Selection.v
ip/utiie_cpu/hdl/Pipeline_Reg.v
ip/utiie_cpu/hdl/Pipeline_S2_Regs.v
ip/utiie_cpu/hdl/Pipeline_S3_Regs.v
ip/utiie_cpu/hdl/Predecode_Instruction.v
ip/utiie_cpu/hdl/Program_Counter.v
ip/utiie_cpu/hdl/Register_File.v
ip/utiie_cpu/hdl/Reg_Write_Addr_Mux.v
ip/utiie_cpu/hdl/Reg_Write_Data_Mux.v
ip/utiie_cpu/hdl/Reg_Write_Enable.v
ip/utiie_cpu/hdl/Shifter_Unit.v
ip/utiie_cpu/hdl/Stage_Four.v
ip/utiie_cpu/hdl/Stage_One.v
ip/utiie_cpu/hdl/Stage_Three.v
ip/utiie_cpu/hdl/Stage_Two.v
ip/utiie_cpu/hdl/UT_II_Economy_cpu.v
ip/utiie_cpu/mif/
ip/utiie_cpu/mif/decoder_memory.mif
ip/utiie_cpu/mif/reg_memory.mif
ip/utiie_cpu/modelsim dat/
ip/utiie_cpu/modelsim dat/decoder_memory.dat
ip/utiie_cpu/modelsim dat/reg_memory.dat
ip/vectcpu.sdc
ip/vect_cpu/
ip/vect_cpu/gen_loadaddr_roms.m
ip/vect_cpu/hdl/
ip/vect_cpu/hdl/altMultAccum.v
ip/vect_cpu/hdl/ALU.v
ip/vect_cpu/hdl/components.v
ip/vect_cpu/hdl/config_def.v
ip/vect_cpu/hdl/config_def_auto.v
ip/vect_cpu/hdl/define.v
ip/vect_cpu/hdl/flagunit.v
ip/vect_cpu/hdl/isa_def.v
ip/vect_cpu/hdl/lanemult_mf.v
ip/vect_cpu/hdl/loadAddrGenerator.v
ip/vect_cpu/hdl/loadstoreAddrCount.v
ip/vect_cpu/hdl/loadstoreController.v
ip/vect_cpu/hdl/lsu_wraddr_q.v
ip/vect_cpu/hdl/MACunit.v
ip/vect_cpu/hdl/mathmacros.v
ip/vect_cpu/hdl/memIF.v
ip/vect_cpu/hdl/memreadIF.v
ip/vect_cpu/hdl/memwriteIF.v
ip/vect_cpu/hdl/memxbar.v
ip/vect_cpu/hdl/mem_order_q.v
ip/vect_cpu/hdl/NElemRemainder_rom_init.v
ip/vect_cpu/hdl/NElemXfer_rom_init.v
ip/vect_cpu/hdl/scalarToVectorQ.v
ip/vect_cpu/hdl/shiftdecode.v
ip/vect_cpu/hdl/shifter.v
ip/vect_cpu/hdl/storeAddrGen.v
ip/vect_cpu/hdl/storeCtr_fillreg.v
ip/vect_cpu/hdl/storeCtr_writemem.v
ip/vect_cpu/hdl/VectCPU.v
ip/vect_cpu/hdl/vectorToScalarQ_data_sel.v
ip/vect_cpu/hdl/vflagreg_mf.v
ip/vect_cpu/hdl/VLane_controller.v
ip/vect_cpu/hdl/VLane_datapath.v
ip/vect_cpu/hdl/vlane_enable_decode.v
ip/vect_cpu/hdl/VLane_group.v
ip/vect_cpu/hdl/VLane_loadstoreDataQ.v
ip/vect_cpu/hdl/VLane_storeFlagQ.v
ip/vect_cpu/hdl/VLane_top.v
ip/vect_cpu/hdl/VPU_controller.v
ip/vect_cpu/hdl/VPU_controlreg.v
ip/vect_cpu/hdl/VPU_decode.v
ip/vect_cpu/hdl/VPU_decode_s3.v
ip/vect_cpu/hdl/VPU_decode_s4.v
ip/vect_cpu/hdl/VPU_hazard_detection.v
ip/vect_cpu/hdl/VPU_pipeline_regs.v
ip/vect_cpu/hdl/VPU_predecode.v
ip/vect_cpu/hdl/VPU_top.v
ip/vect_cpu/mif/
ip/vect_cpu/mif/control_reg_other.mif
ip/vect_cpu/mif/NElemRemainder_rom.mif
ip/vect_cpu/mif/NElemXfer_rom.mif
ip/vect_cpu/modelsim/
ip/vect_cpu/modelsim/control_reg_other.dat
ip/vect_cpu/modelsim/control_reg_other.hex
ip/vect_cpu/modelsim/decoder_memory.dat
ip/vect_cpu/modelsim/dmem_init.hex
ip/vect_cpu/modelsim/example_disassemble.asm
ip/vect_cpu/modelsim/example_disassemble.txt
ip/vect_cpu/modelsim/imem.asm
ip/vect_cpu/modelsim/imem.hex
ip/vect_cpu/modelsim/NElemRemainder_rom.dat
ip/vect_cpu/modelsim/NElemXfer_rom.dat
ip/vect_cpu/modelsim/parse_state_dump.tcl
ip/vect_cpu/modelsim/reg_memory.dat
ip/vect_cpu/modelsim/scalarreg.hex
ip/vect_cpu/modelsim/simulation.cr.mti
ip/vect_cpu/modelsim/simulation.mpf
ip/vect_cpu/modelsim/standard_tests_16.asm
ip/vect_cpu/modelsim/standard_tests_8.asm
ip/vect_cpu/modelsim/test output/
ip/vect_cpu/modelsim/test output/V16M8/
ip/vect_cpu/modelsim/test output/V16M8/store_trace.stores.txt
ip/vect_cpu/modelsim/test output/V16M8/vrf_dump_summary.arith.txt
ip/vect_cpu/modelsim/test output/V16M8/vrf_dump_summary.compare.txt
ip/vect_cpu/modelsim/test output/V16M8/vrf_dump_summary.loads.txt
ip/vect_cpu/modelsim/test output/V16M8/vrf_dump_summary.logical.txt
ip/vect_cpu/mo
scalarcore.stp
VectCPU_sys.qip
VectCPU_sys.qpf
VectCPU_sys.qsf
VectCPU_sys.sdc
assembler/
assembler/README.txt
assembler/src/
assembler/src/binutils/
assembler/src/binutils/gas/
assembler/src/binutils/gas/config/
assembler/src/binutils/gas/config/tc-nios2.c
assembler/src/binutils/include/
assembler/src/binutils/include/opcode/
assembler/src/binutils/include/opcode/nios2.h
assembler/src/binutils/opcodes/
assembler/src/binutils/opcodes/nios2-opc.c
assembler/Test/
assembler/Test/test.asm
assembler/Test/vector_testsuite_results.log
assembler/Test/vector_testsuite_results2.log
assembler/Test/vector_testsuite_results3.log
assembler/Test/vector_testsuite_results4.log
assembler/Test/vector_testsuite_results5(final).log
assembler/Test/v_assembler_test.s
assembler/Test/v_assembler_test_extracomma.s
assembler/Test/v_assembler_test_wrongreg.s
README.txt
VectCPU_sys.sopc
ip/
ip/utiie_cpu/
ip/utiie_cpu/cb_generator.pl
ip/utiie_cpu/class.ptf
ip/utiie_cpu/hdl/
ip/utiie_cpu/hdl/Adder_w_Comparator.v
ip/utiie_cpu/hdl/ALU_Logic.v
ip/utiie_cpu/hdl/Branch_Logic.v
ip/utiie_cpu/hdl/Control_Registers.v
ip/utiie_cpu/hdl/Control_Unit.v
ip/utiie_cpu/hdl/Datapath.v
ip/utiie_cpu/hdl/Decoder_Logic.v
ip/utiie_cpu/hdl/Instruction_Fetch_Unit.v
ip/utiie_cpu/hdl/Instr_Register.v
ip/utiie_cpu/hdl/isa_def.v
ip/utiie_cpu/hdl/Logic_Unit.v
ip/utiie_cpu/hdl/Memory_Address_Align.v
ip/utiie_cpu/hdl/Memory_Byteenable.v
ip/utiie_cpu/hdl/Memory_Data_In_Align.v
ip/utiie_cpu/hdl/Memory_Data_Out_Align.v
ip/utiie_cpu/hdl/Next_PC_Shifter_Selection.v
ip/utiie_cpu/hdl/OpA_Selection.v
ip/utiie_cpu/hdl/OpB_Imm_Selection.v
ip/utiie_cpu/hdl/Pipeline_Reg.v
ip/utiie_cpu/hdl/Pipeline_S2_Regs.v
ip/utiie_cpu/hdl/Pipeline_S3_Regs.v
ip/utiie_cpu/hdl/Predecode_Instruction.v
ip/utiie_cpu/hdl/Program_Counter.v
ip/utiie_cpu/hdl/Register_File.v
ip/utiie_cpu/hdl/Reg_Write_Addr_Mux.v
ip/utiie_cpu/hdl/Reg_Write_Data_Mux.v
ip/utiie_cpu/hdl/Reg_Write_Enable.v
ip/utiie_cpu/hdl/Shifter_Unit.v
ip/utiie_cpu/hdl/Stage_Four.v
ip/utiie_cpu/hdl/Stage_One.v
ip/utiie_cpu/hdl/Stage_Three.v
ip/utiie_cpu/hdl/Stage_Two.v
ip/utiie_cpu/hdl/UT_II_Economy_cpu.v
ip/utiie_cpu/mif/
ip/utiie_cpu/mif/decoder_memory.mif
ip/utiie_cpu/mif/reg_memory.mif
ip/utiie_cpu/modelsim dat/
ip/utiie_cpu/modelsim dat/decoder_memory.dat
ip/utiie_cpu/modelsim dat/reg_memory.dat
ip/vectcpu.sdc
ip/vect_cpu/
ip/vect_cpu/gen_loadaddr_roms.m
ip/vect_cpu/hdl/
ip/vect_cpu/hdl/altMultAccum.v
ip/vect_cpu/hdl/ALU.v
ip/vect_cpu/hdl/components.v
ip/vect_cpu/hdl/config_def.v
ip/vect_cpu/hdl/config_def_auto.v
ip/vect_cpu/hdl/define.v
ip/vect_cpu/hdl/flagunit.v
ip/vect_cpu/hdl/isa_def.v
ip/vect_cpu/hdl/lanemult_mf.v
ip/vect_cpu/hdl/loadAddrGenerator.v
ip/vect_cpu/hdl/loadstoreAddrCount.v
ip/vect_cpu/hdl/loadstoreController.v
ip/vect_cpu/hdl/lsu_wraddr_q.v
ip/vect_cpu/hdl/MACunit.v
ip/vect_cpu/hdl/mathmacros.v
ip/vect_cpu/hdl/memIF.v
ip/vect_cpu/hdl/memreadIF.v
ip/vect_cpu/hdl/memwriteIF.v
ip/vect_cpu/hdl/memxbar.v
ip/vect_cpu/hdl/mem_order_q.v
ip/vect_cpu/hdl/NElemRemainder_rom_init.v
ip/vect_cpu/hdl/NElemXfer_rom_init.v
ip/vect_cpu/hdl/scalarToVectorQ.v
ip/vect_cpu/hdl/shiftdecode.v
ip/vect_cpu/hdl/shifter.v
ip/vect_cpu/hdl/storeAddrGen.v
ip/vect_cpu/hdl/storeCtr_fillreg.v
ip/vect_cpu/hdl/storeCtr_writemem.v
ip/vect_cpu/hdl/VectCPU.v
ip/vect_cpu/hdl/vectorToScalarQ_data_sel.v
ip/vect_cpu/hdl/vflagreg_mf.v
ip/vect_cpu/hdl/VLane_controller.v
ip/vect_cpu/hdl/VLane_datapath.v
ip/vect_cpu/hdl/vlane_enable_decode.v
ip/vect_cpu/hdl/VLane_group.v
ip/vect_cpu/hdl/VLane_loadstoreDataQ.v
ip/vect_cpu/hdl/VLane_storeFlagQ.v
ip/vect_cpu/hdl/VLane_top.v
ip/vect_cpu/hdl/VPU_controller.v
ip/vect_cpu/hdl/VPU_controlreg.v
ip/vect_cpu/hdl/VPU_decode.v
ip/vect_cpu/hdl/VPU_decode_s3.v
ip/vect_cpu/hdl/VPU_decode_s4.v
ip/vect_cpu/hdl/VPU_hazard_detection.v
ip/vect_cpu/hdl/VPU_pipeline_regs.v
ip/vect_cpu/hdl/VPU_predecode.v
ip/vect_cpu/hdl/VPU_top.v
ip/vect_cpu/mif/
ip/vect_cpu/mif/control_reg_other.mif
ip/vect_cpu/mif/NElemRemainder_rom.mif
ip/vect_cpu/mif/NElemXfer_rom.mif
ip/vect_cpu/modelsim/
ip/vect_cpu/modelsim/control_reg_other.dat
ip/vect_cpu/modelsim/control_reg_other.hex
ip/vect_cpu/modelsim/decoder_memory.dat
ip/vect_cpu/modelsim/dmem_init.hex
ip/vect_cpu/modelsim/example_disassemble.asm
ip/vect_cpu/modelsim/example_disassemble.txt
ip/vect_cpu/modelsim/imem.asm
ip/vect_cpu/modelsim/imem.hex
ip/vect_cpu/modelsim/NElemRemainder_rom.dat
ip/vect_cpu/modelsim/NElemXfer_rom.dat
ip/vect_cpu/modelsim/parse_state_dump.tcl
ip/vect_cpu/modelsim/reg_memory.dat
ip/vect_cpu/modelsim/scalarreg.hex
ip/vect_cpu/modelsim/simulation.cr.mti
ip/vect_cpu/modelsim/simulation.mpf
ip/vect_cpu/modelsim/standard_tests_16.asm
ip/vect_cpu/modelsim/standard_tests_8.asm
ip/vect_cpu/modelsim/test output/
ip/vect_cpu/modelsim/test output/V16M8/
ip/vect_cpu/modelsim/test output/V16M8/store_trace.stores.txt
ip/vect_cpu/modelsim/test output/V16M8/vrf_dump_summary.arith.txt
ip/vect_cpu/modelsim/test output/V16M8/vrf_dump_summary.compare.txt
ip/vect_cpu/modelsim/test output/V16M8/vrf_dump_summary.loads.txt
ip/vect_cpu/modelsim/test output/V16M8/vrf_dump_summary.logical.txt
ip/vect_cpu/mo
本网站为编程资源及源代码搜集、介绍的搜索网站，版权归原作者所有！ 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.