文件名称:timer_VHDL
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- 上传时间:2013-07-10
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文件大小:258.54kb
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实现对秒信号分频到ms级,通过异步串口接收时分秒信号,将这些信号连同ms信号并送给同步串口-Achieve the second signal is divided into ms level, through an asynchronous serial receiver, hour signal, signals and these signals are sent along with ms synchronous serial
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下载文件列表
timer_VHDL/.compxlib.log
timer_VHDL/.lso
timer_VHDL/Analysis 1.twx
timer_VHDL/asyn_uart/uart.v
timer_VHDL/asyn_uart/uart_transceiver.v
timer_VHDL/asyn_uart/vsim.wlf
timer_VHDL/asyn_uart/wave_auart.do
timer_VHDL/clock_topology.twr
timer_VHDL/iseconfig/sys_top_module.xreport
timer_VHDL/iseconfig/timer_count.xreport
timer_VHDL/iseconfig/timer_design.projectmgr
timer_VHDL/iseconfig/uart.xreport
timer_VHDL/mr_ad.vhd.bak
timer_VHDL/pa.fromNcd.tcl
timer_VHDL/planAhead.ngc2edif.log
timer_VHDL/rz_DivArrUns.vhd
timer_VHDL/signal_syn.cmd_log
timer_VHDL/signal_syn.lso
timer_VHDL/signal_syn.ngc
timer_VHDL/signal_syn.ngr
timer_VHDL/signal_syn.prj
timer_VHDL/signal_syn.stx
timer_VHDL/signal_syn.syr
timer_VHDL/signal_syn.vhd
timer_VHDL/signal_syn.xst
timer_VHDL/signal_syn_envsettings.html
timer_VHDL/signal_syn_summary.html
timer_VHDL/signal_syn_vhdl.prj
timer_VHDL/signal_syn_xst.xrpt
timer_VHDL/syn_uart/syn_uart.vhd
timer_VHDL/syn_uart/vish_stacktrace.vstf
timer_VHDL/syn_uart/vsim.wlf
timer_VHDL/syn_uart/wave.do
timer_VHDL/syn_uart.cmd_log
timer_VHDL/syn_uart.lso
timer_VHDL/syn_uart.ngc
timer_VHDL/syn_uart.ngr
timer_VHDL/syn_uart.prj
timer_VHDL/syn_uart.stx
timer_VHDL/syn_uart.syr
timer_VHDL/syn_uart.xst
timer_VHDL/syn_uart_envsettings.html
timer_VHDL/syn_uart_summary.html
timer_VHDL/syn_uart_vhdl.prj
timer_VHDL/syn_uart_xst.xrpt
timer_VHDL/system.ucf
timer_VHDL/system.ucf.bak
timer_VHDL/sys_top_module.bgn
timer_VHDL/sys_top_module.bit
timer_VHDL/sys_top_module.bld
timer_VHDL/sys_top_module.cmd_log
timer_VHDL/sys_top_module.drc
timer_VHDL/sys_top_module.lso
timer_VHDL/sys_top_module.pad
timer_VHDL/sys_top_module.par
timer_VHDL/sys_top_module.pcf
timer_VHDL/sys_top_module.prj
timer_VHDL/sys_top_module.ptwx
timer_VHDL/sys_top_module.stx
timer_VHDL/sys_top_module.syr
timer_VHDL/sys_top_module.twr
timer_VHDL/sys_top_module.twx
timer_VHDL/sys_top_module.unroutes
timer_VHDL/sys_top_module.ut
timer_VHDL/sys_top_module.vhd
timer_VHDL/sys_top_module.vhd.bak
timer_VHDL/sys_top_module.xpi
timer_VHDL/sys_top_module.xst
timer_VHDL/sys_top_module_bitgen.xwbt
timer_VHDL/sys_top_module_envsettings.html
timer_VHDL/sys_top_module_fpga_editor.log
timer_VHDL/sys_top_module_map.map
timer_VHDL/sys_top_module_map.mrp
timer_VHDL/sys_top_module_map.ncd
timer_VHDL/sys_top_module_map.xrpt
timer_VHDL/sys_top_module_ngdbuild.xrpt
timer_VHDL/sys_top_module_pad.csv
timer_VHDL/sys_top_module_summary.html
timer_VHDL/sys_top_module_summary.xml
timer_VHDL/sys_top_module_usage.xml
timer_VHDL/sys_top_module_vhdl.prj
timer_VHDL/sys_top_module_xst.xrpt
timer_VHDL/timer_count.cmd_log
timer_VHDL/timer_count.lso
timer_VHDL/timer_count.prj
timer_VHDL/timer_count.stx
timer_VHDL/timer_count.syr
timer_VHDL/timer_count.vhd
timer_VHDL/timer_count.xst
timer_VHDL/timer_count_envsettings.html
timer_VHDL/timer_count_summary.html
timer_VHDL/timer_count_vhdl.prj
timer_VHDL/timer_count_xst.xrpt
timer_VHDL/timer_design.gise
timer_VHDL/timer_design.xise
timer_VHDL/uart.cmd_log
timer_VHDL/uart.lso
timer_VHDL/uart.ngc
timer_VHDL/uart.prj
timer_VHDL/uart.stx
timer_VHDL/uart.syr
timer_VHDL/uart.xst
timer_VHDL/uart_envsettings.html
timer_VHDL/uart_summary.html
timer_VHDL/uart_transceiver.cmd_log
timer_VHDL/uart_transceiver.lso
timer_VHDL/uart_transceiver.ngc
timer_VHDL/uart_transceiver.ngr
timer_VHDL/uart_transceiver.prj
timer_VHDL/uart_transceiver.stx
timer_VHDL/uart_transceiver.syr
timer_VHDL/uart_transceiver.xst
timer_VHDL/uart_transceiver_envsettings.html
timer_VHDL/uart_transceiver_summary.html
timer_VHDL/uart_transceiver_xst.xrpt
timer_VHDL/uart_xst.xrpt
timer_VHDL/usage_statistics_webtalk.html
timer_VHDL/vsim.wlf
timer_VHDL/wave.do
timer_VHDL/wavesys.do
timer_VHDL/wave_timer_count.do
timer_VHDL/webtalk.log
timer_VHDL/webtalk_pn.xml
timer_VHDL/xlnx_auto_0_xdb/cst.xbcd
timer_VHDL/asyn_uart
timer_VHDL/doc
timer_VHDL/iseconfig
timer_VHDL/syn_uart
timer_VHDL/xlnx_auto_0_xdb
timer_VHDL
timer_VHDL/.lso
timer_VHDL/Analysis 1.twx
timer_VHDL/asyn_uart/uart.v
timer_VHDL/asyn_uart/uart_transceiver.v
timer_VHDL/asyn_uart/vsim.wlf
timer_VHDL/asyn_uart/wave_auart.do
timer_VHDL/clock_topology.twr
timer_VHDL/iseconfig/sys_top_module.xreport
timer_VHDL/iseconfig/timer_count.xreport
timer_VHDL/iseconfig/timer_design.projectmgr
timer_VHDL/iseconfig/uart.xreport
timer_VHDL/mr_ad.vhd.bak
timer_VHDL/pa.fromNcd.tcl
timer_VHDL/planAhead.ngc2edif.log
timer_VHDL/rz_DivArrUns.vhd
timer_VHDL/signal_syn.cmd_log
timer_VHDL/signal_syn.lso
timer_VHDL/signal_syn.ngc
timer_VHDL/signal_syn.ngr
timer_VHDL/signal_syn.prj
timer_VHDL/signal_syn.stx
timer_VHDL/signal_syn.syr
timer_VHDL/signal_syn.vhd
timer_VHDL/signal_syn.xst
timer_VHDL/signal_syn_envsettings.html
timer_VHDL/signal_syn_summary.html
timer_VHDL/signal_syn_vhdl.prj
timer_VHDL/signal_syn_xst.xrpt
timer_VHDL/syn_uart/syn_uart.vhd
timer_VHDL/syn_uart/vish_stacktrace.vstf
timer_VHDL/syn_uart/vsim.wlf
timer_VHDL/syn_uart/wave.do
timer_VHDL/syn_uart.cmd_log
timer_VHDL/syn_uart.lso
timer_VHDL/syn_uart.ngc
timer_VHDL/syn_uart.ngr
timer_VHDL/syn_uart.prj
timer_VHDL/syn_uart.stx
timer_VHDL/syn_uart.syr
timer_VHDL/syn_uart.xst
timer_VHDL/syn_uart_envsettings.html
timer_VHDL/syn_uart_summary.html
timer_VHDL/syn_uart_vhdl.prj
timer_VHDL/syn_uart_xst.xrpt
timer_VHDL/system.ucf
timer_VHDL/system.ucf.bak
timer_VHDL/sys_top_module.bgn
timer_VHDL/sys_top_module.bit
timer_VHDL/sys_top_module.bld
timer_VHDL/sys_top_module.cmd_log
timer_VHDL/sys_top_module.drc
timer_VHDL/sys_top_module.lso
timer_VHDL/sys_top_module.pad
timer_VHDL/sys_top_module.par
timer_VHDL/sys_top_module.pcf
timer_VHDL/sys_top_module.prj
timer_VHDL/sys_top_module.ptwx
timer_VHDL/sys_top_module.stx
timer_VHDL/sys_top_module.syr
timer_VHDL/sys_top_module.twr
timer_VHDL/sys_top_module.twx
timer_VHDL/sys_top_module.unroutes
timer_VHDL/sys_top_module.ut
timer_VHDL/sys_top_module.vhd
timer_VHDL/sys_top_module.vhd.bak
timer_VHDL/sys_top_module.xpi
timer_VHDL/sys_top_module.xst
timer_VHDL/sys_top_module_bitgen.xwbt
timer_VHDL/sys_top_module_envsettings.html
timer_VHDL/sys_top_module_fpga_editor.log
timer_VHDL/sys_top_module_map.map
timer_VHDL/sys_top_module_map.mrp
timer_VHDL/sys_top_module_map.ncd
timer_VHDL/sys_top_module_map.xrpt
timer_VHDL/sys_top_module_ngdbuild.xrpt
timer_VHDL/sys_top_module_pad.csv
timer_VHDL/sys_top_module_summary.html
timer_VHDL/sys_top_module_summary.xml
timer_VHDL/sys_top_module_usage.xml
timer_VHDL/sys_top_module_vhdl.prj
timer_VHDL/sys_top_module_xst.xrpt
timer_VHDL/timer_count.cmd_log
timer_VHDL/timer_count.lso
timer_VHDL/timer_count.prj
timer_VHDL/timer_count.stx
timer_VHDL/timer_count.syr
timer_VHDL/timer_count.vhd
timer_VHDL/timer_count.xst
timer_VHDL/timer_count_envsettings.html
timer_VHDL/timer_count_summary.html
timer_VHDL/timer_count_vhdl.prj
timer_VHDL/timer_count_xst.xrpt
timer_VHDL/timer_design.gise
timer_VHDL/timer_design.xise
timer_VHDL/uart.cmd_log
timer_VHDL/uart.lso
timer_VHDL/uart.ngc
timer_VHDL/uart.prj
timer_VHDL/uart.stx
timer_VHDL/uart.syr
timer_VHDL/uart.xst
timer_VHDL/uart_envsettings.html
timer_VHDL/uart_summary.html
timer_VHDL/uart_transceiver.cmd_log
timer_VHDL/uart_transceiver.lso
timer_VHDL/uart_transceiver.ngc
timer_VHDL/uart_transceiver.ngr
timer_VHDL/uart_transceiver.prj
timer_VHDL/uart_transceiver.stx
timer_VHDL/uart_transceiver.syr
timer_VHDL/uart_transceiver.xst
timer_VHDL/uart_transceiver_envsettings.html
timer_VHDL/uart_transceiver_summary.html
timer_VHDL/uart_transceiver_xst.xrpt
timer_VHDL/uart_xst.xrpt
timer_VHDL/usage_statistics_webtalk.html
timer_VHDL/vsim.wlf
timer_VHDL/wave.do
timer_VHDL/wavesys.do
timer_VHDL/wave_timer_count.do
timer_VHDL/webtalk.log
timer_VHDL/webtalk_pn.xml
timer_VHDL/xlnx_auto_0_xdb/cst.xbcd
timer_VHDL/asyn_uart
timer_VHDL/doc
timer_VHDL/iseconfig
timer_VHDL/syn_uart
timer_VHDL/xlnx_auto_0_xdb
timer_VHDL
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