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文件名称:AlteraFPGA_CPLDdesignbasic

  • 所属分类：
    嵌入式/单片机编程
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2008-10-13
  • 文件大小：
    4.1mb
  • 已下载：
    1次
  • 提 供 者：
    l****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

一本老师推荐的经典的VHDL覆盖基础的入门书籍，内容翔实充分
(系统自动生成,下载前可以参看下载内容)

下载文件列表

光盘使用说明.doc
Example-b8-3/示例说明.doc
Example-b8-1/示例说明.doc
Example-b8-2/示例说明.doc
Example-b8-4/示例说明.doc
Example-b8-5/示例说明.doc
Example-b8-6/示例说明.doc
Example-b4-2/示例说明.doc
Example-b4-1/示例说明.doc
Example-b3-1/示例说明.doc
Example-b8-1/Altera_lib_files/220model.txt
Example-b8-2/Altera_lib_files/220model.txt
Example-b8-1/Altera_lib_files/altera_mf.txt
Example-b8-2/Altera_lib_files/altera_mf.txt
Example-b8-1/source/dpram8x32_waveforms.html
Example-b8-2/source/dpram8x32_waveforms.html
Example-b4-2/Solution/IP_ENC/ENC.html
Example-b3-1/uart_regs/core/myfifo_10_waveforms.html
Example-b3-1/uart_regs/core/myfifo_8_waveforms.html
Example-b8-6/Synplify_Pro/rev_2/stderr.log
Example-b8-6/Synplify_Pro/rev_3/stderr.log
Example-b8-6/Synplify_Pro/rev_2/stdout.log
Example-b8-6/Synplify_Pro/rev_3/stdout.log
Example-b3-1/uart_regs/dev/cmp_state.ini
Example-b8-1/pll_ram/cmp_state.ini
Example-b8-2/pll_ram/cmp_state.ini
Example-b8-1/timing_sim/work/exp/verilog.asm
Example-b8-2/timing_sim/work/exp/verilog.asm
Example-b8-1/timing_sim/work/carry/verilog.asm
Example-b8-1/timing_sim/work/cascade/verilog.asm
Example-b8-1/timing_sim/work/global/verilog.asm
Example-b8-2/timing_sim/work/carry/verilog.asm
Example-b8-2/timing_sim/work/cascade/verilog.asm
Example-b8-2/timing_sim/work/global/verilog.asm
Example-b8-1/timing_sim/work/lcell/verilog.asm
Example-b8-2/timing_sim/work/lcell/verilog.asm
Example-b8-1/timing_sim/work/@p@r@i@m_@d@f@f@e/verilog.asm
Example-b8-2/timing_sim/work/@p@r@i@m_@d@f@f@e/verilog.asm
Example-b8-1/timing_sim/work/carry_sum/verilog.asm
Example-b8-2/timing_sim/work/carry_sum/verilog.asm
Example-b8-1/timing_sim/work/and1/verilog.asm
Example-b8-2/timing_sim/work/and1/verilog.asm
Example-b8-1/timing_sim/work/io_buf_opdrn/verilog.asm
Example-b8-2/timing_sim/work/io_buf_opdrn/verilog.asm
Example-b8-1/timing_sim/work/io_buf_tri/verilog.asm
Example-b8-2/timing_sim/work/io_buf_tri/verilog.asm
Example-b8-3/work/counter/verilog.asm
Example-b8-1/timing_sim/work/nmux21/verilog.asm
Example-b8-1/timing_sim/work/b5mux21/verilog.asm
Example-b8-1/timing_sim/work/bmux21/verilog.asm
Example-b8-2/timing_sim/work/b5mux21/verilog.asm
Example-b8-2/timing_sim/work/bmux21/verilog.asm
Example-b8-1/timing_sim/work/b17mux21/verilog.asm
Example-b8-2/timing_sim/work/b17mux21/verilog.asm
Example-b8-1/timing_sim/work/stratix_crcblock/verilog.asm
Example-b8-1/timing_sim/work/hcstratix_crcblock/verilog.asm
Example-b8-2/timing_sim/work/hcstratix_crcblock/verilog.asm
Example-b8-1/timing_sim/work/dffp/verilog.asm
Example-b8-2/timing_sim/work/dffp/verilog.asm
Example-b8-1/timing_sim/work/pll_reg/verilog.asm
Example-b8-1/timing_sim/work/@m@f_pll_reg/verilog.asm
Example-b8-2/timing_sim/work/@m@f_pll_reg/verilog.asm
Example-b8-1/timing_sim/work/lpm_constant/verilog.asm
Example-b8-2/timing_sim/work/lpm_constant/verilog.asm
Example-b8-1/timing_sim/work/hcstratix_ram_clear/verilog.asm
Example-b8-1/timing_sim/work/stratix_ram_clear/verilog.asm
Example-b8-2/timing_sim/work/hcstratix_ram_clear/verilog.asm
Example-b8-5/demo_project/work/test_counter/verilog.asm
Example-b8-1/timing_sim/work/lpm_outpad/verilog.asm
Example-b8-1/timing_sim/work/lpm_inpad/verilog.asm
Example-b8-1/timing_sim/work/lpm_inv/verilog.asm
Example-b8-1/timing_sim/work/oper_decoder/verilog.asm
Example-b8-1/timing_sim/work/and16/verilog.asm
Example-b8-2/timing_sim/work/and16/verilog.asm
Example-b8-1/timing_sim/work/mux21/verilog.asm
Example-b8-1/timing_sim/work/stratix_jtag/verilog.asm
Example-b8-1/timing_sim/work/hcstratix_jtag/verilog.asm
Example-b8-2/timing_sim/work/hcstratix_jtag/verilog.asm
Example-b8-1/timing_sim/work/arm_n_cntr/verilog.asm
Example-b8-2/timing_sim/work/arm_n_cntr/verilog.asm
Example-b8-1/timing_sim/work/oper_mux/verilog.asm
Example-b8-5/demo_project/work/counter/verilog.asm
Example-b8-1/timing_sim/work/n_cntr/verilog.asm
Example-b8-1/timing_sim/work/m_cntr/verilog.asm
Example-b8-1/timing_sim/work/stx_n_cntr/verilog.asm
Example-b8-1/timing_sim/work/lpm_bipad/verilog.asm
Example-b8-2/timing_sim/work/lpm_bipad/verilog.asm
Example-b8-1/timing_sim/work/arm_m_cntr/verilog.asm
Example-b8-2/timing_sim/work/arm_m_cntr/verilog.asm
Example-b8-1/func_sim/work/pll_ram/verilog.asm
Example-b8-2/func_sim/work/pll_ram/verilog.asm
Example-b8-1/timing_sim/work/latch/verilog.asm
Example-b8-2/timing_sim/work/latch/verilog.asm
Example-b8-1/timing_sim/work/stx_m_cntr/verilog.asm
Example-b8-1/timing_sim/work/mux41/verilog.asm
Example-b8-1/timing_sim/work/lpm_abs/verilog.asm
Example-b8-2/timing_sim/work/lpm_abs/verilog.asm
Example-b8-1/timing_sim/work/oper_selector/verilog.asm
Example-b8-1/timing_sim/work/tri_bus/verilog.asm
Example-b8-1/timing_sim/work/a_graycounter/verilog.asm
Example-b8-2/timing_sim/work/a_graycounter/verilog.asm
Example-b8-1/func_sim/work/dpram8x32/verilog.asm
Example-b8-2/func_sim/work/dpram8x32/verilog.asm
Example-b8-1/timing_sim/work/dffe/verilog.asm
Example-b8-2/timing_sim/work/dffe/verilog.asm
Example-b8-1/func_sim/work/pll_ram_tb/verilog.asm
Example-b8-1/timing_sim/work/pll_ram_tb/verilog.asm
Example-b8-2/func_sim/work/pll_ram_tb/verilog.asm
Example-b8-1/timing_sim/work/oper_mult/verilog.asm
Example-b

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