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文件名称:caitiao

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  • 上传时间:
    2013-07-19
  • 文件大小:
    4.44mb
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介绍说明--下载内容来自于网络,使用问题请自行百度

QuartusII软件写的四条竖彩条信号,通过ADV7171芯片转成模拟信号在监视屏上显示。-The color bar signal which are writen by VHDL ,with the data of the signal converted to analog signal by ADV7171 ,are showed on TV monitor .
(系统自动生成,下载前可以参看下载内容)

下载文件列表

caitiao/
caitiao/.sopc_builder/
caitiao/.sopc_builder/filters.xml
caitiao/Design.asm.rpt
caitiao/Design.cdf
caitiao/Design.done
caitiao/Design.dpf
caitiao/Design.eda.rpt
caitiao/Design.fit.rpt
caitiao/Design.fit.smsg
caitiao/Design.fit.summary
caitiao/Design.flow.rpt
caitiao/Design.map.rpt
caitiao/Design.map.summary
caitiao/Design.pin
caitiao/Design.qpf
caitiao/Design.qsf
caitiao/Design.qws
caitiao/Design.sim.rpt
caitiao/Design.sof
caitiao/Design.sta.rpt
caitiao/Design.sta.summary
caitiao/Design.vhd
caitiao/Design.vhd.bak
caitiao/Design.vwf
caitiao/I2C_ADV7171.vhd
caitiao/I2C_ADV7171.vhd.bak
caitiao/I2C_TVP5150.vhd
caitiao/I2C_TVP5150.vhd.bak
caitiao/Re_毕设答疑.zip
caitiao/SAV_check.vhd
caitiao/SAV_check.vhd.bak
caitiao/caitiao.vhd
caitiao/caitiao.vhd.bak
caitiao/converter.vhd
caitiao/converter.vhd.bak
caitiao/db/
caitiao/db/Design.(0).cnf.cdb
caitiao/db/Design.(0).cnf.hdb
caitiao/db/Design.(1).cnf.cdb
caitiao/db/Design.(1).cnf.hdb
caitiao/db/Design.(2).cnf.cdb
caitiao/db/Design.(2).cnf.hdb
caitiao/db/Design.(3).cnf.cdb
caitiao/db/Design.(3).cnf.hdb
caitiao/db/Design.(4).cnf.cdb
caitiao/db/Design.(4).cnf.hdb
caitiao/db/Design.(5).cnf.cdb
caitiao/db/Design.(5).cnf.hdb
caitiao/db/Design.(6).cnf.cdb
caitiao/db/Design.(6).cnf.hdb
caitiao/db/Design.asm.qmsg
caitiao/db/Design.asm_labs.ddb
caitiao/db/Design.cbx.xml
caitiao/db/Design.cmp.bpm
caitiao/db/Design.cmp.cdb
caitiao/db/Design.cmp.ecobp
caitiao/db/Design.cmp.hdb
caitiao/db/Design.cmp.kpt
caitiao/db/Design.cmp.logdb
caitiao/db/Design.cmp.rdb
caitiao/db/Design.cmp_merge.kpt
caitiao/db/Design.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
caitiao/db/Design.cuda_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
caitiao/db/Design.db_info
caitiao/db/Design.eco.cdb
caitiao/db/Design.eda.qmsg
caitiao/db/Design.eds_overflow
caitiao/db/Design.fit.qmsg
caitiao/db/Design.hier_info
caitiao/db/Design.hif
caitiao/db/Design.lpc.html
caitiao/db/Design.lpc.rdb
caitiao/db/Design.lpc.txt
caitiao/db/Design.map.bpm
caitiao/db/Design.map.cdb
caitiao/db/Design.map.ecobp
caitiao/db/Design.map.hdb
caitiao/db/Design.map.kpt
caitiao/db/Design.map.logdb
caitiao/db/Design.map.qmsg
caitiao/db/Design.map_bb.cdb
caitiao/db/Design.map_bb.hdb
caitiao/db/Design.map_bb.logdb
caitiao/db/Design.pre_map.cdb
caitiao/db/Design.pre_map.hdb
caitiao/db/Design.rtlv.hdb
caitiao/db/Design.rtlv_sg.cdb
caitiao/db/Design.rtlv_sg_swap.cdb
caitiao/db/Design.sgdiff.cdb
caitiao/db/Design.sgdiff.hdb
caitiao/db/Design.sim.cvwf
caitiao/db/Design.sim.hdb
caitiao/db/Design.sim.qmsg
caitiao/db/Design.sim.rdb
caitiao/db/Design.sld_design_entry.sci
caitiao/db/Design.sld_design_entry_dsc.sci
caitiao/db/Design.smp_dump.txt
caitiao/db/Design.sta.qmsg
caitiao/db/Design.sta.rdb
caitiao/db/Design.sta_cmp.6_slow_1200mv_85c.tdb
caitiao/db/Design.syn_hier_info
caitiao/db/Design.tis_db_list.ddb
caitiao/db/Design.tiscmp.fast_1200mv_0c.ddb
caitiao/db/Design.tiscmp.slow_1200mv_0c.ddb
caitiao/db/Design.tiscmp.slow_1200mv_85c.ddb
caitiao/db/Design.tmw_info
caitiao/db/Design_global_asgn_op.abo
caitiao/db/prev_cmp_Design.asm.qmsg
caitiao/db/prev_cmp_Design.eda.qmsg
caitiao/db/prev_cmp_Design.fit.qmsg
caitiao/db/prev_cmp_Design.map.qmsg
caitiao/db/prev_cmp_Design.qmsg
caitiao/db/prev_cmp_Design.sim.qmsg
caitiao/db/prev_cmp_Design.sta.qmsg
caitiao/db/wed.wsf
caitiao/filter.vhd
caitiao/filter.vhd.bak
caitiao/filter_compile.do
caitiao/filter_synplify.tcl
caitiao/filter_tb.vhd
caitiao/filter_tb_compile.do
caitiao/filter_tb_sim.do
caitiao/incremental_db/
caitiao/incremental_db/README
caitiao/incremental_db/compiled_partitions/
caitiao/incremental_db/compiled_partitions/Design.root_partition.cmp.atm
caitiao/incremental_db/compiled_partitions/Design.root_partition.cmp.dfp
caitiao/incremental_db/compiled_partitions/Design.root_partition.cmp.hdbx
caitiao/incremental_db/compiled_partitions/Design.root_partition.cmp.kpt
caitiao/incremental_db/compiled_partitions/Design.root_partition.cmp.logdb
caitiao/incremental_db/compiled_partitions/Design.root_partition.cmp.rcf
caitiao/incremental_db/compiled_partitions/Design.root_partition.map.atm
caitiao/incremental_db/compiled_partitions/Design.root_partition.map.dpi
caitiao/incremental_db/compiled_partitions/Design.root_partition.map.hdbx
caitiao/incremental_db/compiled_partitions/Design.root_partition.map.kpt
caitiao/license.txt
caitiao/readme.txt
caitiao/reg8.vhd
caitiao/s_store.vhd
caitiao/s_store.vhd.bak
caitiao/simulation/
caitiao/simulation/modelsim/
caitiao/simulation/modelsim/Design.sft
caitiao/simulation/modelsim/Design.vho
caitiao/simulation/modelsim/Design_6_1200mv_0c_slow.vho
caitiao/simulation/modelsim/Design_6_1200mv_0c_vhd_slow.sdo
caitiao/simulation/modelsim/Design_6_1200mv_85c_slow.vho
caitiao/simulation/modelsim/Design_6_1200mv_85c_vhd_slow.sdo
caitiao/simulation/modelsim/Design_min_1200mv_0c_fast.vho
caitiao/simulation/modelsim/Design_min_1200mv_0c_vhd_fast.sdo
caitiao/simulation/modelsim/Design_modelsim.xrf
caitiao/simulation/modelsim/Design_vhd.sdo
caitiao/sopc_builder_log.txt
caitiao/write_blank.vhd
caitiao/write_blank.vhd.bak

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