文件名称:blank
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- 上传时间：2013-07-19
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文件大小：6.28mb
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介绍说明－－下载内容来自于网络，使用问题请自行百度
监控摄像头传入数据，通过芯片TVP5150转换成数字信号，其中sav_check.vhd检测帧头，converter.vhd将信号转换成Y，Cb，Cr格式，最后write_blank.vhd重新组建完整数字信号，最后通过ADV7171转成模拟信号输出到监视器上。这中间，可以对Y做各种图像处理，如滤波处理，均衡处理，只需要在converter之后添加处理文件即可。-Surveillance camera incoming data through the chip TVP5150 converted into a digital signal, wherein the detection of the header sav_check.vhd, converter.vhd the signal into Y, Cb, Cr format, and finally re-establishment of full write_blank.vhd digital signals, and finally by transfer ADV7171 the analog signal is output to the monitor. This is the middle, you can do all kinds of Y image processing, such as filtering, equalization, only need to be added after the converter processing files.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
blank/
blank/Design.asm.rpt
blank/Design.cdf
blank/Design.done
blank/Design.dpf
blank/Design.eda.rpt
blank/Design.fit.rpt
blank/Design.fit.smsg
blank/Design.fit.summary
blank/Design.flow.rpt
blank/Design.map.rpt
blank/Design.map.summary
blank/Design.pin
blank/Design.qpf
blank/Design.qsf
blank/Design.qws
blank/Design.sof
blank/Design.sta.rpt
blank/Design.sta.summary
blank/Design.vhd
blank/Design.vhd.bak
blank/I2C_ADV7171.vhd
blank/I2C_ADV7171.vhd.bak
blank/I2C_TVP5150.vhd
blank/I2C_TVP5150.vhd.bak
blank/Re_毕设答疑.zip
blank/SAV_check.vhd
blank/SAV_check.vhd.bak
blank/converter.vhd
blank/converter.vhd.bak
blank/db/
blank/db/Design.(0).cnf.cdb
blank/db/Design.(0).cnf.hdb
blank/db/Design.(1).cnf.cdb
blank/db/Design.(1).cnf.hdb
blank/db/Design.(2).cnf.cdb
blank/db/Design.(2).cnf.hdb
blank/db/Design.(3).cnf.cdb
blank/db/Design.(3).cnf.hdb
blank/db/Design.(4).cnf.cdb
blank/db/Design.(4).cnf.hdb
blank/db/Design.(5).cnf.cdb
blank/db/Design.(5).cnf.hdb
blank/db/Design.(6).cnf.cdb
blank/db/Design.(6).cnf.hdb
blank/db/Design.asm.qmsg
blank/db/Design.asm_labs.ddb
blank/db/Design.cbx.xml
blank/db/Design.cmp.bpm
blank/db/Design.cmp.cdb
blank/db/Design.cmp.ecobp
blank/db/Design.cmp.hdb
blank/db/Design.cmp.kpt
blank/db/Design.cmp.logdb
blank/db/Design.cmp.rdb
blank/db/Design.cmp_merge.kpt
blank/db/Design.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
blank/db/Design.cuda_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
blank/db/Design.db_info
blank/db/Design.eco.cdb
blank/db/Design.eda.qmsg
blank/db/Design.fit.qmsg
blank/db/Design.hier_info
blank/db/Design.hif
blank/db/Design.lpc.html
blank/db/Design.lpc.rdb
blank/db/Design.lpc.txt
blank/db/Design.map.bpm
blank/db/Design.map.cdb
blank/db/Design.map.ecobp
blank/db/Design.map.hdb
blank/db/Design.map.kpt
blank/db/Design.map.logdb
blank/db/Design.map.qmsg
blank/db/Design.map_bb.cdb
blank/db/Design.map_bb.hdb
blank/db/Design.map_bb.logdb
blank/db/Design.pre_map.cdb
blank/db/Design.pre_map.hdb
blank/db/Design.rtlv.hdb
blank/db/Design.rtlv_sg.cdb
blank/db/Design.rtlv_sg_swap.cdb
blank/db/Design.sgdiff.cdb
blank/db/Design.sgdiff.hdb
blank/db/Design.sld_design_entry.sci
blank/db/Design.sld_design_entry_dsc.sci
blank/db/Design.smp_dump.txt
blank/db/Design.sta.qmsg
blank/db/Design.sta.rdb
blank/db/Design.sta_cmp.6_slow_1200mv_85c.tdb
blank/db/Design.syn_hier_info
blank/db/Design.tis_db_list.ddb
blank/db/Design.tiscmp.fast_1200mv_0c.ddb
blank/db/Design.tiscmp.slow_1200mv_0c.ddb
blank/db/Design.tiscmp.slow_1200mv_85c.ddb
blank/db/Design.tmw_info
blank/db/Design_global_asgn_op.abo
blank/db/prev_cmp_Design.asm.qmsg
blank/db/prev_cmp_Design.eda.qmsg
blank/db/prev_cmp_Design.fit.qmsg
blank/db/prev_cmp_Design.map.qmsg
blank/db/prev_cmp_Design.qmsg
blank/db/prev_cmp_Design.sta.qmsg
blank/filter.vhd
blank/filter.vhd.bak
blank/filter_compile.do
blank/filter_synplify.tcl
blank/filter_tb.vhd
blank/filter_tb_compile.do
blank/filter_tb_sim.do
blank/incremental_db/
blank/incremental_db/README
blank/incremental_db/compiled_partitions/
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.atm
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.dfp
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.hdbx
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.kpt
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.logdb
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.rcf
blank/incremental_db/compiled_partitions/Design.root_partition.map.atm
blank/incremental_db/compiled_partitions/Design.root_partition.map.dpi
blank/incremental_db/compiled_partitions/Design.root_partition.map.hdbx
blank/incremental_db/compiled_partitions/Design.root_partition.map.kpt
blank/license.txt
blank/readme.txt
blank/reg8.vhd
blank/s_store.vhd
blank/s_store.vhd.bak
blank/sel.vhd
blank/simulation/
blank/simulation/modelsim/
blank/simulation/modelsim/Design.sft
blank/simulation/modelsim/Design.vho
blank/simulation/modelsim/Design_6_1200mv_0c_slow.vho
blank/simulation/modelsim/Design_6_1200mv_0c_vhd_slow.sdo
blank/simulation/modelsim/Design_6_1200mv_85c_slow.vho
blank/simulation/modelsim/Design_6_1200mv_85c_vhd_slow.sdo
blank/simulation/modelsim/Design_min_1200mv_0c_fast.vho
blank/simulation/modelsim/Design_min_1200mv_0c_vhd_fast.sdo
blank/simulation/modelsim/Design_modelsim.xrf
blank/simulation/modelsim/Design_vhd.sdo
blank/tem.vhd
blank/write_blank.vhd
blank/write_blank.vhd.bak
blank/Design.asm.rpt
blank/Design.cdf
blank/Design.done
blank/Design.dpf
blank/Design.eda.rpt
blank/Design.fit.rpt
blank/Design.fit.smsg
blank/Design.fit.summary
blank/Design.flow.rpt
blank/Design.map.rpt
blank/Design.map.summary
blank/Design.pin
blank/Design.qpf
blank/Design.qsf
blank/Design.qws
blank/Design.sof
blank/Design.sta.rpt
blank/Design.sta.summary
blank/Design.vhd
blank/Design.vhd.bak
blank/I2C_ADV7171.vhd
blank/I2C_ADV7171.vhd.bak
blank/I2C_TVP5150.vhd
blank/I2C_TVP5150.vhd.bak
blank/Re_毕设答疑.zip
blank/SAV_check.vhd
blank/SAV_check.vhd.bak
blank/converter.vhd
blank/converter.vhd.bak
blank/db/
blank/db/Design.(0).cnf.cdb
blank/db/Design.(0).cnf.hdb
blank/db/Design.(1).cnf.cdb
blank/db/Design.(1).cnf.hdb
blank/db/Design.(2).cnf.cdb
blank/db/Design.(2).cnf.hdb
blank/db/Design.(3).cnf.cdb
blank/db/Design.(3).cnf.hdb
blank/db/Design.(4).cnf.cdb
blank/db/Design.(4).cnf.hdb
blank/db/Design.(5).cnf.cdb
blank/db/Design.(5).cnf.hdb
blank/db/Design.(6).cnf.cdb
blank/db/Design.(6).cnf.hdb
blank/db/Design.asm.qmsg
blank/db/Design.asm_labs.ddb
blank/db/Design.cbx.xml
blank/db/Design.cmp.bpm
blank/db/Design.cmp.cdb
blank/db/Design.cmp.ecobp
blank/db/Design.cmp.hdb
blank/db/Design.cmp.kpt
blank/db/Design.cmp.logdb
blank/db/Design.cmp.rdb
blank/db/Design.cmp_merge.kpt
blank/db/Design.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
blank/db/Design.cuda_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
blank/db/Design.db_info
blank/db/Design.eco.cdb
blank/db/Design.eda.qmsg
blank/db/Design.fit.qmsg
blank/db/Design.hier_info
blank/db/Design.hif
blank/db/Design.lpc.html
blank/db/Design.lpc.rdb
blank/db/Design.lpc.txt
blank/db/Design.map.bpm
blank/db/Design.map.cdb
blank/db/Design.map.ecobp
blank/db/Design.map.hdb
blank/db/Design.map.kpt
blank/db/Design.map.logdb
blank/db/Design.map.qmsg
blank/db/Design.map_bb.cdb
blank/db/Design.map_bb.hdb
blank/db/Design.map_bb.logdb
blank/db/Design.pre_map.cdb
blank/db/Design.pre_map.hdb
blank/db/Design.rtlv.hdb
blank/db/Design.rtlv_sg.cdb
blank/db/Design.rtlv_sg_swap.cdb
blank/db/Design.sgdiff.cdb
blank/db/Design.sgdiff.hdb
blank/db/Design.sld_design_entry.sci
blank/db/Design.sld_design_entry_dsc.sci
blank/db/Design.smp_dump.txt
blank/db/Design.sta.qmsg
blank/db/Design.sta.rdb
blank/db/Design.sta_cmp.6_slow_1200mv_85c.tdb
blank/db/Design.syn_hier_info
blank/db/Design.tis_db_list.ddb
blank/db/Design.tiscmp.fast_1200mv_0c.ddb
blank/db/Design.tiscmp.slow_1200mv_0c.ddb
blank/db/Design.tiscmp.slow_1200mv_85c.ddb
blank/db/Design.tmw_info
blank/db/Design_global_asgn_op.abo
blank/db/prev_cmp_Design.asm.qmsg
blank/db/prev_cmp_Design.eda.qmsg
blank/db/prev_cmp_Design.fit.qmsg
blank/db/prev_cmp_Design.map.qmsg
blank/db/prev_cmp_Design.qmsg
blank/db/prev_cmp_Design.sta.qmsg
blank/filter.vhd
blank/filter.vhd.bak
blank/filter_compile.do
blank/filter_synplify.tcl
blank/filter_tb.vhd
blank/filter_tb_compile.do
blank/filter_tb_sim.do
blank/incremental_db/
blank/incremental_db/README
blank/incremental_db/compiled_partitions/
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.atm
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.dfp
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.hdbx
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.kpt
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.logdb
blank/incremental_db/compiled_partitions/Design.root_partition.cmp.rcf
blank/incremental_db/compiled_partitions/Design.root_partition.map.atm
blank/incremental_db/compiled_partitions/Design.root_partition.map.dpi
blank/incremental_db/compiled_partitions/Design.root_partition.map.hdbx
blank/incremental_db/compiled_partitions/Design.root_partition.map.kpt
blank/license.txt
blank/readme.txt
blank/reg8.vhd
blank/s_store.vhd
blank/s_store.vhd.bak
blank/sel.vhd
blank/simulation/
blank/simulation/modelsim/
blank/simulation/modelsim/Design.sft
blank/simulation/modelsim/Design.vho
blank/simulation/modelsim/Design_6_1200mv_0c_slow.vho
blank/simulation/modelsim/Design_6_1200mv_0c_vhd_slow.sdo
blank/simulation/modelsim/Design_6_1200mv_85c_slow.vho
blank/simulation/modelsim/Design_6_1200mv_85c_vhd_slow.sdo
blank/simulation/modelsim/Design_min_1200mv_0c_fast.vho
blank/simulation/modelsim/Design_min_1200mv_0c_vhd_fast.sdo
blank/simulation/modelsim/Design_modelsim.xrf
blank/simulation/modelsim/Design_vhd.sdo
blank/tem.vhd
blank/write_blank.vhd
blank/write_blank.vhd.bak
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