文件名称:part1
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- 上传时间:2013-07-22
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文件大小:137.45kb
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a 4-bit synchronous counter using T-Flip Flops and AND gates in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
part1/cmp_state.ini
part1/db/
part1/db/lab3_part1(0).cnf.cdb
part1/db/lab3_part1(0).cnf.hdb
part1/db/lab3_part1(1).cnf.cdb
part1/db/lab3_part1(1).cnf.hdb
part1/db/lab3_part1(2).cnf.cdb
part1/db/lab3_part1(2).cnf.hdb
part1/db/lab3_part1(3).cnf.cdb
part1/db/lab3_part1(3).cnf.hdb
part1/db/lab3_part1.asm.qmsg
part1/db/lab3_part1.cmp.cdb
part1/db/lab3_part1.cmp.ddb
part1/db/lab3_part1.cmp.hdb
part1/db/lab3_part1.cmp.rdb
part1/db/lab3_part1.cmp.tdb
part1/db/lab3_part1.csf.qmsg
part1/db/lab3_part1.db_info
part1/db/lab3_part1.fit.qmsg
part1/db/lab3_part1.frm.hdb
part1/db/lab3_part1.fsf.qmsg
part1/db/lab3_part1.hif
part1/db/lab3_part1.lab3_part1.sld_design_entry.sci
part1/db/lab3_part1.map.cdb
part1/db/lab3_part1.map.hdb
part1/db/lab3_part1.map.qmsg
part1/db/lab3_part1.pre_map.hdb
part1/db/lab3_part1.project.hdb
part1/db/lab3_part1.rtlv.hdb
part1/db/lab3_part1.rtlv_sg.cdb
part1/db/lab3_part1.rtlv_sg_swap.cdb
part1/db/lab3_part1.sgdiff.cdb
part1/db/lab3_part1.sgdiff.hdb
part1/db/lab3_part1.sim.hdb
part1/db/lab3_part1.sim.qmsg
part1/db/lab3_part1.sim.rdb
part1/db/lab3_part1.tan.qmsg
part1/db/lab3_part1_cmp.qrpt
part1/db/lab3_part1_hier_info
part1/db/lab3_part1_sim.qrpt
part1/db/lab3_part1_syn_hier_info
part1/db/lab3_part1-sim.vwf
part1/lab3_part1.asm.rpt
part1/lab3_part1.cdf
part1/lab3_part1.done
part1/lab3_part1.fit.eqn
part1/lab3_part1.fit.rpt
part1/lab3_part1.flow.rpt
part1/lab3_part1.map.eqn
part1/lab3_part1.map.rpt
part1/lab3_part1.pin
part1/lab3_part1.pof
part1/lab3_part1.qpf
part1/lab3_part1.qsf
part1/lab3_part1.qws
part1/lab3_part1.sim.rpt
part1/lab3_part1.tan.rpt
part1/lab3_part1.tan.summary
part1/lab3_part1.v
part1/lab3_part1.vwf
part1/seg_digit.v
part1/seg_ten.v
part1/sim.cfg
part1/tff0.v
part1/db/
part1/db/lab3_part1(0).cnf.cdb
part1/db/lab3_part1(0).cnf.hdb
part1/db/lab3_part1(1).cnf.cdb
part1/db/lab3_part1(1).cnf.hdb
part1/db/lab3_part1(2).cnf.cdb
part1/db/lab3_part1(2).cnf.hdb
part1/db/lab3_part1(3).cnf.cdb
part1/db/lab3_part1(3).cnf.hdb
part1/db/lab3_part1.asm.qmsg
part1/db/lab3_part1.cmp.cdb
part1/db/lab3_part1.cmp.ddb
part1/db/lab3_part1.cmp.hdb
part1/db/lab3_part1.cmp.rdb
part1/db/lab3_part1.cmp.tdb
part1/db/lab3_part1.csf.qmsg
part1/db/lab3_part1.db_info
part1/db/lab3_part1.fit.qmsg
part1/db/lab3_part1.frm.hdb
part1/db/lab3_part1.fsf.qmsg
part1/db/lab3_part1.hif
part1/db/lab3_part1.lab3_part1.sld_design_entry.sci
part1/db/lab3_part1.map.cdb
part1/db/lab3_part1.map.hdb
part1/db/lab3_part1.map.qmsg
part1/db/lab3_part1.pre_map.hdb
part1/db/lab3_part1.project.hdb
part1/db/lab3_part1.rtlv.hdb
part1/db/lab3_part1.rtlv_sg.cdb
part1/db/lab3_part1.rtlv_sg_swap.cdb
part1/db/lab3_part1.sgdiff.cdb
part1/db/lab3_part1.sgdiff.hdb
part1/db/lab3_part1.sim.hdb
part1/db/lab3_part1.sim.qmsg
part1/db/lab3_part1.sim.rdb
part1/db/lab3_part1.tan.qmsg
part1/db/lab3_part1_cmp.qrpt
part1/db/lab3_part1_hier_info
part1/db/lab3_part1_sim.qrpt
part1/db/lab3_part1_syn_hier_info
part1/db/lab3_part1-sim.vwf
part1/lab3_part1.asm.rpt
part1/lab3_part1.cdf
part1/lab3_part1.done
part1/lab3_part1.fit.eqn
part1/lab3_part1.fit.rpt
part1/lab3_part1.flow.rpt
part1/lab3_part1.map.eqn
part1/lab3_part1.map.rpt
part1/lab3_part1.pin
part1/lab3_part1.pof
part1/lab3_part1.qpf
part1/lab3_part1.qsf
part1/lab3_part1.qws
part1/lab3_part1.sim.rpt
part1/lab3_part1.tan.rpt
part1/lab3_part1.tan.summary
part1/lab3_part1.v
part1/lab3_part1.vwf
part1/seg_digit.v
part1/seg_ten.v
part1/sim.cfg
part1/tff0.v
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