文件名称:CPU
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文件大小:1.76mb
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基于FPGA控制的ASIC CPU系统设计,全是用VERILOG代码编写,可以做加减乘除运算
-FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
-FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
(系统自动生成,下载前可以参看下载内容)
下载文件列表
CPU/PIC16C57用户手册.pdf
CPU/RISC8 CPU 结构 (risc8).gif
CPU/RISC8 CPU 说明书.html
CPU/TB/alu.v
CPU/TB/basic.asm
CPU/TB/BASIC.HEX
CPU/TB/basic.rom
CPU/TB/CPU.cr.mti
CPU/TB/CPU.mpf
CPU/TB/cpu.v
CPU/TB/dds.asm
CPU/TB/DDS.HEX
CPU/TB/dds.rom
CPU/TB/dram.v
CPU/TB/exp.v
CPU/TB/hex2v.c
CPU/TB/idec.v
CPU/TB/pram.v
CPU/TB/regs.v
CPU/TB/risc8.vcd
CPU/TB/runit
CPU/TB/sindata.c
CPU/TB/sindata.hex
CPU/TB/tcl_stacktrace.txt
CPU/TB/test.v
CPU/TB/test.v.bak
CPU/TB/test.v~
CPU/TB/vsim.wlf
CPU/TB/work/alu/verilog.asm
CPU/TB/work/alu/_primary.dat
CPU/TB/work/alu/_primary.vhd
CPU/TB/work/cpu/verilog.asm
CPU/TB/work/cpu/_primary.dat
CPU/TB/work/cpu/_primary.vhd
CPU/TB/work/dram/verilog.asm
CPU/TB/work/dram/_primary.dat
CPU/TB/work/dram/_primary.vhd
CPU/TB/work/exp/verilog.asm
CPU/TB/work/exp/_primary.dat
CPU/TB/work/exp/_primary.vhd
CPU/TB/work/idec/verilog.asm
CPU/TB/work/idec/_primary.dat
CPU/TB/work/idec/_primary.vhd
CPU/TB/work/pram/verilog.asm
CPU/TB/work/pram/_primary.dat
CPU/TB/work/pram/_primary.vhd
CPU/TB/work/regs/verilog.asm
CPU/TB/work/regs/_primary.dat
CPU/TB/work/regs/_primary.vhd
CPU/TB/work/test/verilog.asm
CPU/TB/work/test/_primary.dat
CPU/TB/work/test/_primary.vhd
CPU/TB/work/_info
CPU/TB/work/alu
CPU/TB/work/cpu
CPU/TB/work/dram
CPU/TB/work/exp
CPU/TB/work/idec
CPU/TB/work/pram
CPU/TB/work/regs
CPU/TB/work/test
CPU/TB/work
CPU/TB
CPU
CPU/RISC8 CPU 结构 (risc8).gif
CPU/RISC8 CPU 说明书.html
CPU/TB/alu.v
CPU/TB/basic.asm
CPU/TB/BASIC.HEX
CPU/TB/basic.rom
CPU/TB/CPU.cr.mti
CPU/TB/CPU.mpf
CPU/TB/cpu.v
CPU/TB/dds.asm
CPU/TB/DDS.HEX
CPU/TB/dds.rom
CPU/TB/dram.v
CPU/TB/exp.v
CPU/TB/hex2v.c
CPU/TB/idec.v
CPU/TB/pram.v
CPU/TB/regs.v
CPU/TB/risc8.vcd
CPU/TB/runit
CPU/TB/sindata.c
CPU/TB/sindata.hex
CPU/TB/tcl_stacktrace.txt
CPU/TB/test.v
CPU/TB/test.v.bak
CPU/TB/test.v~
CPU/TB/vsim.wlf
CPU/TB/work/alu/verilog.asm
CPU/TB/work/alu/_primary.dat
CPU/TB/work/alu/_primary.vhd
CPU/TB/work/cpu/verilog.asm
CPU/TB/work/cpu/_primary.dat
CPU/TB/work/cpu/_primary.vhd
CPU/TB/work/dram/verilog.asm
CPU/TB/work/dram/_primary.dat
CPU/TB/work/dram/_primary.vhd
CPU/TB/work/exp/verilog.asm
CPU/TB/work/exp/_primary.dat
CPU/TB/work/exp/_primary.vhd
CPU/TB/work/idec/verilog.asm
CPU/TB/work/idec/_primary.dat
CPU/TB/work/idec/_primary.vhd
CPU/TB/work/pram/verilog.asm
CPU/TB/work/pram/_primary.dat
CPU/TB/work/pram/_primary.vhd
CPU/TB/work/regs/verilog.asm
CPU/TB/work/regs/_primary.dat
CPU/TB/work/regs/_primary.vhd
CPU/TB/work/test/verilog.asm
CPU/TB/work/test/_primary.dat
CPU/TB/work/test/_primary.vhd
CPU/TB/work/_info
CPU/TB/work/alu
CPU/TB/work/cpu
CPU/TB/work/dram
CPU/TB/work/exp
CPU/TB/work/idec
CPU/TB/work/pram
CPU/TB/work/regs
CPU/TB/work/test
CPU/TB/work
CPU/TB
CPU
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