一个32位的5 级流水线处理器。在构架这个处理器的结构过程中是按照MIPS指令进行各个流水段的功能划分，并且在处理各种相关的时候参照了手头上的一个GCC_MIPS的C 语言编译器，因此支持MIPS 1指令系统。编译器的支持使这个核心有了实用价值，这个核心可以应用于各种嵌入式系统设计，代替常规的单片机实现片上系统，还可以在一个芯片里加入多个内核并且灵活的总线连接实现多处理器设计。-A 32-bit pipelined processor 5. In the framework of this processor architecture is based on the MIPS instruction process for each pipeline segment, function, and in dealing with a variety of related reference to have on hand when a GCC_MIPS C language compiler, and therefore supports MIPS 1 instruction. Compiler support to make this core has practical value, the core can be applied to a variety of embedded system design, instead of the conventional single-chip system on a chip, you can also add multiple cores in a single chip and flexible bus connection to multi-processing