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文件名称:LatticeMico8_v3_1_VHDL

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
  • 上传时间：
    2013-08-13
  • 文件大小：
    1.34mb
  • 已下载：
    0次
  • 提 供 者：
    史****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

LATTICE 公司的开放的8位CPU核.-Open 8bit cpu IP from Lattice.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

LatticeMico8_v3_1_VHDL/models/
LatticeMico8_v3_1_VHDL/models/e2/
LatticeMico8_v3_1_VHDL/models/e2/sim/
LatticeMico8_v3_1_VHDL/models/e2/sim/ORCACOMP.vhd
LatticeMico8_v3_1_VHDL/models/e2/sim/ORCA_CMB.vhd
LatticeMico8_v3_1_VHDL/models/e2/sim/ORCA_CNT.vhd
LatticeMico8_v3_1_VHDL/models/e2/sim/ORCA_IO.vhd
LatticeMico8_v3_1_VHDL/models/e2/sim/ORCA_LUT.vhd
LatticeMico8_v3_1_VHDL/models/e2/sim/ORCA_MEM.vhd
LatticeMico8_v3_1_VHDL/models/e2/sim/ORCA_MISC.vhd
LatticeMico8_v3_1_VHDL/models/e2/sim/ORCA_SEQ.vhd
LatticeMico8_v3_1_VHDL/models/e2/sim/pmi_def.vhd
LatticeMico8_v3_1_VHDL/models/e2/sim/prom.vhd
LatticeMico8_v3_1_VHDL/models/e2/syn/
LatticeMico8_v3_1_VHDL/models/e2/syn/ec.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/
LatticeMico8_v3_1_VHDL/models/pmi_work/@add@sign/
LatticeMico8_v3_1_VHDL/models/pmi_work/@add@sign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/@add@sign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/@add@sign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/@add@un@sign/
LatticeMico8_v3_1_VHDL/models/pmi_work/@add@un@sign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/@add@un@sign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/@add@un@sign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@add@sub/
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@add@sub/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@add@sub/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@add@sub/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@sign/
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@sign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@sign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@sign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@sign@pipe/
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@sign@pipe/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@sign@pipe/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@sign@pipe/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@un@sign/
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@un@sign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@un@sign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@un@sign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@un@sign@pipe/
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@un@sign@pipe/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@un@sign@pipe/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/@mult@un@sign@pipe/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/@sub@sign/
LatticeMico8_v3_1_VHDL/models/pmi_work/@sub@sign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/@sub@sign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/@sub@sign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/@sub@un@sign/
LatticeMico8_v3_1_VHDL/models/pmi_work/@sub@un@sign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/@sub@un@sign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/@sub@un@sign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add/
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub/
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub_sign/
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub_sign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub_sign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub_sign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub_unsign/
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub_unsign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub_unsign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_addsub_unsign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add_sign/
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add_sign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add_sign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add_sign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add_unsign/
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add_unsign/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add_unsign/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_add_unsign/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_complex_mult/
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_complex_mult/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_complex_mult/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_complex_mult/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_constant_mult/
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_constant_mult/verilog.psm
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_constant_mult/_primary.dat
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_constant_mult/_primary.vhd
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_counter/
LatticeMico8_v3_1_VHDL/models/pmi_work/pmi_counter/verilog.psm
LatticeMico8_v3_1_VHDL/mod

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