文件名称:xapp882
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- 上传时间：2013-08-14
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This application note describes the implementation of SERDES Framer Interface Level 5
(SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical
Internetworking Forum (OIF). The interface must operate bidirectionally at a payload data rate
of 40 Gb/s with 0–25 forward error correction (FEC) overhead, up to a maximum of 50 Gb/s.
The interface consists of 17 bidirectional GTX transceivers and logic to compensate skew
differences between the transmission paths of the data channels.-This application note describes the implementation of SERDES Framer Interface Level 5
(SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical
Internetworking Forum (OIF). The interface must operate bidirectionally at a payload data rate
of 40 Gb/s with 0–25 forward error correction (FEC) overhead, up to a maximum of 50 Gb/s.
The interface consists of 17 bidirectional GTX transceivers and logic to compensate skew
differences between the transmission paths of the data channels.
(SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical
Internetworking Forum (OIF). The interface must operate bidirectionally at a payload data rate
of 40 Gb/s with 0–25 forward error correction (FEC) overhead, up to a maximum of 50 Gb/s.
The interface consists of 17 bidirectional GTX transceivers and logic to compensate skew
differences between the transmission paths of the data channels.-This application note describes the implementation of SERDES Framer Interface Level 5
(SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical
Internetworking Forum (OIF). The interface must operate bidirectionally at a payload data rate
of 40 Gb/s with 0–25 forward error correction (FEC) overhead, up to a maximum of 50 Gb/s.
The interface consists of 17 bidirectional GTX transceivers and logic to compensate skew
differences between the transmission paths of the data channels.
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下载文件列表
XAPP882/
XAPP882/Bitfile/
XAPP882/Bitfile/sfi5.bit
XAPP882/Chipscope/
XAPP882/Chipscope/chipscope_icon.ngc
XAPP882/Chipscope/chipscope_icon.v
XAPP882/Chipscope/chipscope_ila.ngc
XAPP882/Chipscope/chipscope_ila.v
XAPP882/Chipscope/chipscope_vio.ngc
XAPP882/Chipscope/chipscope_vio.v
XAPP882/Chipscope/SFI5_DEMO.cpj
XAPP882/Design/
XAPP882/Design/counter_128.v
XAPP882/Design/counter_32bit.v
XAPP882/Design/counter_64.v
XAPP882/Design/gtx_wrapper.v
XAPP882/Design/gtx_wrapper_gtx.v
XAPP882/Design/sfi5_if_v6_16bit.v
XAPP882/Design/sfi5_reset_rx.v
XAPP882/Design/sfi5_reset_tx.v
XAPP882/Design/sfi5_rx_barrel_shifter_16bit.v
XAPP882/Design/sfi5_rx_data_sync.v
XAPP882/Design/sfi5_rx_frame_sync.v
XAPP882/Design/sfi5_rx_if_v6_16bit.v
XAPP882/Design/sfi5_tx_deskew_channel.v
XAPP882/Design/tx_sync.v
XAPP882/Hardware_Testbench/
XAPP882/Hardware_Testbench/prbs31_gen.v
XAPP882/Hardware_Testbench/sfi5_ml623_demo.v
XAPP882/Implementation/
XAPP882/Implementation/run_syn
XAPP882/Implementation/sfi5.cmd
XAPP882/Implementation/sfi5.prj
XAPP882/Implementation/sfi5_ml623_demo.ucf
XAPP882/readme.txt
XAPP882/Simulation/
XAPP882/Simulation/SFI5_V6_16BIT_TB.v
XAPP882/Simulation/sim/
XAPP882/Simulation/sim/glbl.v
XAPP882/Simulation/sim/run_sim.do
XAPP882/Simulation/sim/sfi5_wave.do
XAPP882/Simulation/simple_pattern0.v
XAPP882/Simulation/simple_pattern1.v
XAPP882/Bitfile/
XAPP882/Bitfile/sfi5.bit
XAPP882/Chipscope/
XAPP882/Chipscope/chipscope_icon.ngc
XAPP882/Chipscope/chipscope_icon.v
XAPP882/Chipscope/chipscope_ila.ngc
XAPP882/Chipscope/chipscope_ila.v
XAPP882/Chipscope/chipscope_vio.ngc
XAPP882/Chipscope/chipscope_vio.v
XAPP882/Chipscope/SFI5_DEMO.cpj
XAPP882/Design/
XAPP882/Design/counter_128.v
XAPP882/Design/counter_32bit.v
XAPP882/Design/counter_64.v
XAPP882/Design/gtx_wrapper.v
XAPP882/Design/gtx_wrapper_gtx.v
XAPP882/Design/sfi5_if_v6_16bit.v
XAPP882/Design/sfi5_reset_rx.v
XAPP882/Design/sfi5_reset_tx.v
XAPP882/Design/sfi5_rx_barrel_shifter_16bit.v
XAPP882/Design/sfi5_rx_data_sync.v
XAPP882/Design/sfi5_rx_frame_sync.v
XAPP882/Design/sfi5_rx_if_v6_16bit.v
XAPP882/Design/sfi5_tx_deskew_channel.v
XAPP882/Design/tx_sync.v
XAPP882/Hardware_Testbench/
XAPP882/Hardware_Testbench/prbs31_gen.v
XAPP882/Hardware_Testbench/sfi5_ml623_demo.v
XAPP882/Implementation/
XAPP882/Implementation/run_syn
XAPP882/Implementation/sfi5.cmd
XAPP882/Implementation/sfi5.prj
XAPP882/Implementation/sfi5_ml623_demo.ucf
XAPP882/readme.txt
XAPP882/Simulation/
XAPP882/Simulation/SFI5_V6_16BIT_TB.v
XAPP882/Simulation/sim/
XAPP882/Simulation/sim/glbl.v
XAPP882/Simulation/sim/run_sim.do
XAPP882/Simulation/sim/sfi5_wave.do
XAPP882/Simulation/simple_pattern0.v
XAPP882/Simulation/simple_pattern1.v
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