CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程

文件名称:uart_verilog

  • 所属分类:
  • 标签属性:
  • 上传时间:
    2013-08-14
  • 文件大小:
    2.94mb
  • 已下载:
    0次
  • 提 供 者:
  • 相关连接:
  • 下载说明:
    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

Verilog HDL语言编写的uart程序,在别人基础上改动和优化完成,quartus ii 10.0编译通过,可综合,板上仿真通过。将PC机发送的字符串发送回,可一次发送多个字符串。-Verilog HDL language uart program, in others on the basis of changes and optimization is complete, quartus ii 10.0 compiler, integrated, on-board through simulation. The PC sends the string is sent back at once send multiple strings.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart_verilog/db/logic_util_heursitic.dat
uart_verilog/db/prev_cmp_uart.qmsg
uart_verilog/db/uart.(0).cnf.cdb
uart_verilog/db/uart.(0).cnf.hdb
uart_verilog/db/uart.(1).cnf.cdb
uart_verilog/db/uart.(1).cnf.hdb
uart_verilog/db/uart.(2).cnf.cdb
uart_verilog/db/uart.(2).cnf.hdb
uart_verilog/db/uart.(3).cnf.cdb
uart_verilog/db/uart.(3).cnf.hdb
uart_verilog/db/uart.amm.cdb
uart_verilog/db/uart.analyze_file.qmsg
uart_verilog/db/uart.asm.qmsg
uart_verilog/db/uart.asm.rdb
uart_verilog/db/uart.asm_labs.ddb
uart_verilog/db/uart.cbx.xml
uart_verilog/db/uart.cmp.bpm
uart_verilog/db/uart.cmp.cbp
uart_verilog/db/uart.cmp.cdb
uart_verilog/db/uart.cmp.hdb
uart_verilog/db/uart.cmp.kpt
uart_verilog/db/uart.cmp.logdb
uart_verilog/db/uart.cmp.rdb
uart_verilog/db/uart.cmp_merge.kpt
uart_verilog/db/uart.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
uart_verilog/db/uart.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
uart_verilog/db/uart.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
uart_verilog/db/uart.db_info
uart_verilog/db/uart.fit.qmsg
uart_verilog/db/uart.hier_info
uart_verilog/db/uart.hif
uart_verilog/db/uart.idb.cdb
uart_verilog/db/uart.lpc.html
uart_verilog/db/uart.lpc.rdb
uart_verilog/db/uart.lpc.txt
uart_verilog/db/uart.map.bpm
uart_verilog/db/uart.map.cbp
uart_verilog/db/uart.map.cdb
uart_verilog/db/uart.map.hdb
uart_verilog/db/uart.map.kpt
uart_verilog/db/uart.map.logdb
uart_verilog/db/uart.map.qmsg
uart_verilog/db/uart.map_bb.cdb
uart_verilog/db/uart.map_bb.hdb
uart_verilog/db/uart.map_bb.logdb
uart_verilog/db/uart.pre_map.cdb
uart_verilog/db/uart.pre_map.hdb
uart_verilog/db/uart.rtlv.hdb
uart_verilog/db/uart.rtlv_sg.cdb
uart_verilog/db/uart.rtlv_sg_swap.cdb
uart_verilog/db/uart.sgdiff.cdb
uart_verilog/db/uart.sgdiff.hdb
uart_verilog/db/uart.sld_design_entry.sci
uart_verilog/db/uart.sld_design_entry_dsc.sci
uart_verilog/db/uart.smart_action.txt
uart_verilog/db/uart.sta.qmsg
uart_verilog/db/uart.sta.rdb
uart_verilog/db/uart.sta_cmp.7_slow_1200mv_85c.tdb
uart_verilog/db/uart.syn_hier_info
uart_verilog/db/uart.tiscmp.fast_1200mv_0c.ddb
uart_verilog/db/uart.tiscmp.slow_1200mv_0c.ddb
uart_verilog/db/uart.tiscmp.slow_1200mv_85c.ddb
uart_verilog/db/uart.tis_db_list.ddb
uart_verilog/db/uart.tmw_info
uart_verilog/incremental_db/compiled_partitions/uart.db_info
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.cmp.cdb
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.cmp.hdb
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.cmp.kpt
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.cmp.logdb
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.cmp.rcfdb
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.cmp.re.rcfdb
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.map.cdb
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.map.dpi
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.map.hdb
uart_verilog/incremental_db/compiled_partitions/uart.root_partition.map.kpt
uart_verilog/incremental_db/README
uart_verilog/speed_select.v
uart_verilog/uart.asm.rpt
uart_verilog/uart.done
uart_verilog/uart.dpf
uart_verilog/uart.fit.rpt
uart_verilog/uart.fit.smsg
uart_verilog/uart.fit.summary
uart_verilog/uart.flow.rpt
uart_verilog/uart.map.rpt
uart_verilog/uart.map.summary
uart_verilog/uart.pin
uart_verilog/uart.qpf
uart_verilog/uart.qsf
uart_verilog/uart.sof
uart_verilog/uart.sta.rpt
uart_verilog/uart.sta.summary
uart_verilog/uart.v
uart_verilog/uart.v.bak
uart_verilog/uart_rx.v
uart_verilog/uart_rx.v.bak
uart_verilog/uart_tx.v
uart_verilog/uart_tx.v.bak
uart_verilog/incremental_db/compiled_partitions
uart_verilog/db
uart_verilog/incremental_db
uart_verilog

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台,只提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度。更多...
  • 本站已设置防盗链,请勿用迅雷、QQ旋风等下载软件下载资源,下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或换浏览器;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*快速评论: 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内  容:
*验 证 码:
搜珍网 www.dssz.com