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文件名称:UART-FPGA

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-08-19
  • 文件大小：
    9.47mb
  • 已下载：
    0次
  • 提 供 者：
    shenx*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

verilog的UART通信，解决了接受过程中的毛刺问题，将接受和发送两个过程独立开来-The UART verilog communication, solve problems receiving glitches during the process of receiving and sending two separate open
(系统自动生成,下载前可以参看下载内容)

下载文件列表

UART-FPGA/
UART-FPGA/db/
UART-FPGA/db/altsyncram_2hq1.tdf
UART-FPGA/db/altsyncram_as14.tdf
UART-FPGA/db/altsyncram_gs14.tdf
UART-FPGA/db/altsyncram_igq1.tdf
UART-FPGA/db/altsyncram_is14.tdf
UART-FPGA/db/altsyncram_ogq1.tdf
UART-FPGA/db/altsyncram_qgq1.tdf
UART-FPGA/db/altsyncram_qs14.tdf
UART-FPGA/db/cmpr_5cc.tdf
UART-FPGA/db/cmpr_9cc.tdf
UART-FPGA/db/cmpr_acc.tdf
UART-FPGA/db/cntr_2ci.tdf
UART-FPGA/db/cntr_gui.tdf
UART-FPGA/db/cntr_qbi.tdf
UART-FPGA/db/cntr_sbi.tdf
UART-FPGA/db/cntr_tbi.tdf
UART-FPGA/db/cntr_u4j.tdf
UART-FPGA/db/cntr_vbi.tdf
UART-FPGA/db/decode_rqf.tdf
UART-FPGA/db/logic_util_heursitic.dat
UART-FPGA/db/mux_9oc.tdf
UART-FPGA/db/prev_cmp_UART.map.qmsg
UART-FPGA/db/prev_cmp_UART.qmsg
UART-FPGA/db/UART.db_info
UART-FPGA/db/UART.ipinfo
UART-FPGA/db/UART.sld_design_entry.sci
UART-FPGA/greybox_tmp/
UART-FPGA/greybox_tmp/cbx_args.txt
UART-FPGA/incremental_db/
UART-FPGA/incremental_db/compiled_partitions/
UART-FPGA/incremental_db/compiled_partitions/UART.autoh_e4eb1.map.dpi
UART-FPGA/incremental_db/compiled_partitions/UART.autoh_e4eb1.map.kpt
UART-FPGA/incremental_db/compiled_partitions/UART.autoh_e4eb1.map.logdb
UART-FPGA/incremental_db/compiled_partitions/UART.autos_3e921.map.dpi
UART-FPGA/incremental_db/compiled_partitions/UART.autos_3e921.map.kpt
UART-FPGA/incremental_db/compiled_partitions/UART.autos_3e921.map.logdb
UART-FPGA/incremental_db/compiled_partitions/UART.db_info
UART-FPGA/incremental_db/compiled_partitions/UART.root_partition.cmp.dfp
UART-FPGA/incremental_db/compiled_partitions/UART.root_partition.cmp.kpt
UART-FPGA/incremental_db/compiled_partitions/UART.root_partition.cmp.logdb
UART-FPGA/incremental_db/compiled_partitions/UART.root_partition.map.atm
UART-FPGA/incremental_db/compiled_partitions/UART.root_partition.map.dpi
UART-FPGA/incremental_db/compiled_partitions/UART.root_partition.map.hdbx
UART-FPGA/incremental_db/compiled_partitions/UART.root_partition.map.kpt
UART-FPGA/incremental_db/README
UART-FPGA/kk.ppf
UART-FPGA/kk.qip
UART-FPGA/kk.v
UART-FPGA/kk_bb.v
UART-FPGA/PLL.ppf
UART-FPGA/PLL.qip
UART-FPGA/PLL.v
UART-FPGA/pll1.cmp
UART-FPGA/pll1.ppf
UART-FPGA/pll1.qip
UART-FPGA/pll1.vhd
UART-FPGA/pll2.ppf
UART-FPGA/pll2.qip
UART-FPGA/pll2.v
UART-FPGA/pll2_bb.v
UART-FPGA/PLLJ_PLLSPE_INFO.txt
UART-FPGA/PLL_bb.v
UART-FPGA/rec.v
UART-FPGA/rec.v.bak
UART-FPGA/send.v
UART-FPGA/send.v.bak
UART-FPGA/serv_req_info.txt
UART-FPGA/simulation/
UART-FPGA/simulation/modelsim/
UART-FPGA/simulation/modelsim/modelsim.ini
UART-FPGA/simulation/modelsim/msim_transcript
UART-FPGA/simulation/modelsim/rtl_work/
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t/
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t/verilog.prw
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t/verilog.psm
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t/_primary.dat
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t/_primary.dbs
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t/_primary.vhd
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t_@t@o@p/
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t_@t@o@p/verilog.prw
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t_@t@o@p/verilog.psm
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t_@t@o@p/_primary.dat
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t_@t@o@p/_primary.dbs
UART-FPGA/simulation/modelsim/rtl_work/@u@a@r@t_@t@o@p/_primary.vhd
UART-FPGA/simulation/modelsim/rtl_work/kk/
UART-FPGA/simulation/modelsim/rtl_work/kk/verilog.prw
UART-FPGA/simulation/modelsim/rtl_work/kk/verilog.psm
UART-FPGA/simulation/modelsim/rtl_work/kk/_primary.dat
UART-FPGA/simulation/modelsim/rtl_work/kk/_primary.dbs
UART-FPGA/simulation/modelsim/rtl_work/kk/_primary.vhd
UART-FPGA/simulation/modelsim/rtl_work/rec/
UART-FPGA/simulation/modelsim/rtl_work/rec/verilog.prw
UART-FPGA/simulation/modelsim/rtl_work/rec/verilog.psm
UART-FPGA/simulation/modelsim/rtl_work/rec/_primary.dat
UART-FPGA/simulation/modelsim/rtl_work/rec/_primary.dbs
UART-FPGA/simulation/modelsim/rtl_work/rec/_primary.vhd
UART-FPGA/simulation/modelsim/rtl_work/send/
UART-FPGA/simulation/modelsim/rtl_work/send/verilog.prw
UART-FPGA/simulation/modelsim/rtl_work/send/verilog.psm
UART-FPGA/simulation/modelsim/rtl_work/send/_primary.dat
UART-FPGA/simulation/modelsim/rtl_work/send/_primary.dbs
UART-FPGA/simulation/modelsim/rtl_work/send/_primary.vhd
UART-FPGA/simulation/modelsim/rtl_work/_info
UART-FPGA/simulation/modelsim/rtl_work/_temp/
UART-FPGA/simulation/modelsim/rtl_work/_vmake
UART-FPGA/simulation/modelsim/UART.sft
UART-FPGA/simulation/modelsim/UART.vho
UART-FPGA/simulation/modelsim/UART.vo
UART-FPGA/simulation/modelsim/UART_6_1200mv_0c_slow.vo
UART-FPGA/simulation/modelsim/UART_6_1200mv_0c_v_slow.sdo
UART-FPGA/simulation/modelsim/UART_6_1200mv_85c_slow.vo
UART-FPGA/simulation/modelsim/UART_6_1200mv_85c_v_slow.sdo
UART-FPGA/simulation/modelsim/UART_fast.vo
UART-FPGA/simulation/modelsim/UART_min_1200mv_0c_fast.vo
UART-FPGA/simulation/modelsim/UART_min_1200mv_0c_v_fast.sdo
UART-FPGA/simulation/modelsim/UART_modelsim.xrf
UART-FPGA/simulation/modelsim/UART_run_msim_rtl_verilog.do
UART-FPGA/simulation/modelsim/UART_run_msim_rtl_verilog.do.bak
UART-FPGA/simulation/modelsim/UART_ru

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