RAM/db/altsyncram_2s21.tdf
RAM/db/altsyncram_j7a1.tdf
RAM/db/logic_util_heursitic.dat
RAM/db/prev_cmp_ram.qmsg
RAM/db/ram.(0).cnf.cdb
RAM/db/ram.(0).cnf.hdb
RAM/db/ram.(1).cnf.cdb
RAM/db/ram.(1).cnf.hdb
RAM/db/ram.(2).cnf.cdb
RAM/db/ram.(2).cnf.hdb
RAM/db/ram.(3).cnf.cdb
RAM/db/ram.(3).cnf.hdb
RAM/db/ram.(4).cnf.cdb
RAM/db/ram.(4).cnf.hdb
RAM/db/ram.(5).cnf.cdb
RAM/db/ram.(5).cnf.hdb
RAM/db/ram.(6).cnf.cdb
RAM/db/ram.(6).cnf.hdb
RAM/db/ram.(7).cnf.cdb
RAM/db/ram.(7).cnf.hdb
RAM/db/ram.(8).cnf.cdb
RAM/db/ram.(8).cnf.hdb
RAM/db/ram.amm.cdb
RAM/db/ram.asm.qmsg
RAM/db/ram.asm.rdb
RAM/db/ram.cbx.xml
RAM/db/ram.cmp.bpm
RAM/db/ram.cmp.cdb
RAM/db/ram.cmp.hdb
RAM/db/ram.cmp.kpt
RAM/db/ram.cmp.logdb
RAM/db/ram.cmp.rdb
RAM/db/ram.cmp0.ddb
RAM/db/ram.cmp_merge.kpt
RAM/db/ram.db_info
RAM/db/ram.eda.qmsg
RAM/db/ram.fit.qmsg
RAM/db/ram.hier_info
RAM/db/ram.hif
RAM/db/ram.idb.cdb
RAM/db/ram.lpc.html
RAM/db/ram.lpc.rdb
RAM/db/ram.lpc.txt
RAM/db/ram.map.bpm
RAM/db/ram.map.cdb
RAM/db/ram.map.hdb
RAM/db/ram.map.kpt
RAM/db/ram.map.logdb
RAM/db/ram.map.qmsg
RAM/db/ram.map_bb.cdb
RAM/db/ram.map_bb.hdb
RAM/db/ram.map_bb.logdb
RAM/db/ram.pre_map.cdb
RAM/db/ram.pre_map.hdb
RAM/db/ram.rtlv.hdb
RAM/db/ram.rtlv_sg.cdb
RAM/db/ram.rtlv_sg_swap.cdb
RAM/db/ram.sgdiff.cdb
RAM/db/ram.sgdiff.hdb
RAM/db/ram.sld_design_entry.sci
RAM/db/ram.sld_design_entry_dsc.sci
RAM/db/ram.smart_action.txt
RAM/db/ram.sta.qmsg
RAM/db/ram.sta.rdb
RAM/db/ram.sta_cmp.8_slow.tdb
RAM/db/ram.syn_hier_info
RAM/db/ram.tis_db_list.ddb
RAM/greybox_tmp/cbx_args.txt
RAM/incremental_db/compiled_partitions/ram.db_info
RAM/incremental_db/compiled_partitions/ram.root_partition.cmp.cdb
RAM/incremental_db/compiled_partitions/ram.root_partition.cmp.dfp
RAM/incremental_db/compiled_partitions/ram.root_partition.cmp.hdb
RAM/incremental_db/compiled_partitions/ram.root_partition.cmp.kpt
RAM/incremental_db/compiled_partitions/ram.root_partition.cmp.logdb
RAM/incremental_db/compiled_partitions/ram.root_partition.cmp.rcfdb
RAM/incremental_db/compiled_partitions/ram.root_partition.map.cdb
RAM/incremental_db/compiled_partitions/ram.root_partition.map.dpi
RAM/incremental_db/compiled_partitions/ram.root_partition.map.hbdb.cdb
RAM/incremental_db/compiled_partitions/ram.root_partition.map.hbdb.hb_info
RAM/incremental_db/compiled_partitions/ram.root_partition.map.hbdb.hdb
RAM/incremental_db/compiled_partitions/ram.root_partition.map.hbdb.sig
RAM/incremental_db/compiled_partitions/ram.root_partition.map.hdb
RAM/incremental_db/compiled_partitions/ram.root_partition.map.kpt
RAM/incremental_db/README
RAM/QQ截图20130821222830.png
RAM/QQ截图20130821223030.png
RAM/ram.asm.rpt
RAM/ram.done
RAM/ram.eda.rpt
RAM/ram.fit.rpt
RAM/ram.fit.smsg
RAM/ram.fit.summary
RAM/ram.flow.rpt
RAM/ram.map.rpt
RAM/ram.map.smsg
RAM/ram.map.summary
RAM/ram.pin
RAM/ram.pof
RAM/ram.qpf
RAM/ram.qsf
RAM/ram.sof
RAM/ram.sta.rpt
RAM/ram.sta.summary
RAM/ram.v
RAM/ram.v.bak
RAM/ram_1.qip
RAM/ram_1.v
RAM/ram_1_bb.v
RAM/ram_nativelink_simulation.rpt
RAM/ram_tb.v
RAM/ram_tb.v.bak
RAM/rom.qip
RAM/rom.v
RAM/rom_bb.v
RAM/simulation/modelsim/modelsim.ini
RAM/simulation/modelsim/msim_transcript
RAM/simulation/modelsim/ram.sft
RAM/simulation/modelsim/ram.vho
RAM/simulation/modelsim/ram_modelsim.xrf
RAM/simulation/modelsim/ram_run_msim_rtl_verilog.do
RAM/simulation/modelsim/ram_run_msim_rtl_verilog.do.bak
RAM/simulation/modelsim/ram_run_msim_rtl_verilog.do.bak1
RAM/simulation/modelsim/ram_run_msim_rtl_verilog.do.bak2
RAM/simulation/modelsim/ram_run_msim_rtl_verilog.do.bak3
RAM/simulation/modelsim/ram_run_msim_rtl_verilog.do.bak4
RAM/simulation/modelsim/ram_run_msim_rtl_verilog.do.bak5
RAM/simulation/modelsim/ram_vhd.sdo
RAM/simulation/modelsim/rtl_work/ram/verilog.prw
RAM/simulation/modelsim/rtl_work/ram/verilog.psm
RAM/simulation/modelsim/rtl_work/ram/_primary.dat
RAM/simulation/modelsim/rtl_work/ram/_primary.dbs
RAM/simulation/modelsim/rtl_work/ram/_primary.vhd
RAM/simulation/modelsim/rtl_work/ram_1/verilog.prw
RAM/simulation/modelsim/rtl_work/ram_1/verilog.psm
RAM/simulation/modelsim/rtl_work/ram_1/_primary.dat
RAM/simulation/modelsim/rtl_work/ram_1/_primary.dbs
RAM/simulation/modelsim/rtl_work/ram_1/_primary.vhd
RAM/simulation/modelsim/rtl_work/ram_tb/verilog.prw
RAM/simulation/modelsim/rtl_work/ram_tb/verilog.psm
RAM/simulation/modelsim/rtl_work/ram_tb/_primary.dat
RAM/simulation/modelsim/rtl_work/ram_tb/_primary.dbs
RAM/simulation/modelsim/rtl_work/ram_tb/_primary.vhd
RAM/simulation/modelsim/rtl_work/rom/verilog.prw
RAM/simulation/modelsim/rtl_work/rom/verilog.psm
RAM/simulation/modelsim/rtl_work/rom/_primary.dat
RAM/simulation/modelsim/rtl_work/rom/_primary.dbs
RAM/simulation/modelsim/rtl_work/rom/_primary.vhd
RAM/simulation/modelsim/rtl_work/_info
RAM/simulation/modelsim/rtl_work/_vmake
RAM/simulation/modelsim/sine.mif
RAM/simulation/modelsim/sine.ver
RAM/simulation/modelsim/vsim.wlf
RAM/sine.mif
RAM/simulation/modelsim/rtl_work/ram
RAM/simulation/modelsim/rtl_work/ram_1
RAM/simulation/modelsim/rtl_work/ram_tb
RAM/simulation/modelsim/rtl_work/rom
RAM/simulation/modelsim/rtl_work/_temp
RAM/simulation/modelsim/rtl_work
RAM/incremental_db/compiled_partitions